Software Defined Radios (SDRs) and Cognitive Radios (CRs) pave the way for next-generation radio technology. They promise versatility, flexibility and cognition which can revolutionize communications systems. However they present greater challenges to the design of radio frequency (RF) front-ends. RF front-ends for the radios in use today are narrow-band in their frequency response and are optimized and tuned to the carrier frequency of interest. SDRs and CRs demand front-ends which are versatile, configurable, tunable and be capable of transmitting and receiving signals with different bandwidths and modulation schemes. Integrating power amplifiers (PAs) with transmitters in CMOS has many advantages and challenges. This thesis deals with the design of an RF transmitter front-end for SDRs and CRs in CMOS. The thesis begins with an introduction to SDRs and the requirements they place on transmitters and the challenges involved in designing them in CMOS. After a brief overview of the existing techniques, the proposed architecture is presented and explained. A digitally intensive transmitter solution is proposed. The transmitter covers a wide frequency range of 750 MHz to 2.5 GHz. The inputs to the proposed transmitter are in-phase and quadrature (I & Q) data bit streams. Multiple stages of up-sampling and filtering are used to remove all spurs in the spectrum such that only the harmonics of the carrier remain. Differential rail-to-rail quadrature clocks are generated from a continuous wave signal at twice the carrier frequency. The clocks are corrected for their duty cycle and quadrature impairments. The heart of the transmitter is an integrated reconfigurable CMOS power amplifier (PA). A methodology to design reconfigurable Class E PAs with a series fixed inductor has been presented. A CMOS power amplifier that can span a wide frequency range with sufficient output power and efficiency, supporting varying envelope complex modulation signals, with good linearity has been designed. Digital pre-distortion (DPD) is used to linearize the PA. The full transmitter and the clock correction blocks have been designed and fabricated in a commercial 130-nm CMOS process and experimentally characterized. The PA delivers a maximum power of 13 dBm with an efficiency of 27% at 1 GHz. While transmitting a 16-QAM signal at 1 GHz, the measured EVM is 4%. It delivers a maximum power of around 11-13 dBm from 750 MHz to 1.5 GHz and up to 6.5 dBm of power till 2.5 GHz. Comparing the proposed system with recently published literature, it can be seen that the proposed design is one of the very few transmitters which has an integrated matching network, tunable across the frequency range. The proposed PA produces the highest output power and with largest efficiency for systems with on-chip output networks.

Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature. The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage. The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work. In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (G_Mc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution. Finally, the Appendix includes recent research work on the analysis and design of g<sbu>m</sub>-boosted common-gate low-noise amplifiers (CG-LNAs). While this topic seems to diverge from the main theme of the dissertation, we believe that the comprehensive analysis and the originality of the circuit design introduced in this work are worth acknowledging. / Ph.D. / While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Shaped Offset Quadrature Phase Shift Keying (SOQPSK) has the advantages of low sidelobes and high detection probability; however, its main lobe has a fixed width set by the number of constellation points. By slightly modifying the modulation scheme, the four constellation points of quadrature shift keying can be changed to M constellation points where M is a power of 2. After this change, the power spectral density (PSD) retains low sidelobes, and the desirable property of being able to detect the signal by integrating over two symbol periods is retained.

In this report, the principles of man-made object detection in satellite images is investigated. An overview of terminology and of how the detection problem is usually solved today is given. A three level system to solve the detection problem is proposed. The main branches of this system handle road, and city detection respectively. To achieve data source flexibility, the Logical Sensor notion is used to model the low level system components. Three Logical Sensors have been implemented and tested on Landsat TM and SPOT XS scenes. These are: BDT (Background Discriminant Transformation) to construct a man-made object property field; Local-orientation for texture estimation and road tracking; Texture estimation using local variance and variance of local orientation. A gradient magnitude measure for road seed generation has also been tested.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / Bit error rate (BER) and bandwidth efficiency of several variations of enhanced Feher patented quadrature phase shift keying (FQPSK) [1] are described. An enhanced FQPSK increases the channel packing density of that of the IRIG 106-00 standardized FQPSK-B by approximately 50% in adjacent channel interference (ACI) environment. As the bandwidth efficiency of FQPSK-B DOUBLES (2×) that of pulse code modulation/Frequency modulation (PCM/FM) [5], the enhanced FQPSK, with a simpler transceiver than FQPSK-B, has a channel packing density of TRIPLE (3×) that of PCM/FM. One of the other enhanced FQPSK prototypes has an end to end system loss of only 0.4 dB at BER=1x10^(-3) and 0.5 dB at BER=1x10^(-4) from ideal linearly amplified QPSK theory. The enhanced FQPSK has a simple architecture, thus is inexpensive and has small size, for ultra high bit rate implementation. With low redundancy forward error correction (FEC) coding which expands the spectrum by approximately 10%, further improvement of about 3-4.5dB E N b o is attained with NLA FQPSK-B and enhanced FQPSK at BER=1x10^(-5) .

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The performance of novel experimental blind equalizers suitable for a large class of applications including telemetry systems and other wireless applications is described. Experimental hardware research of these adaptive patent pending Feher Equalizers (FE) confirms computer simulated data [1]. A two-ray RF selective faded telemetry channel has been simulated. A dynamically changing channel environment with a selective fade rate in the 1Hz to 50Hz range has been constructed by laboratory hardware. The Test and Evaluation (T&E) setup had RF frequency selective dynamic notch depth variations in the Power Spectral Density (PSD) within the band of the signal of up to 15dB. As an illustrative example of the adaptive equalizer capability we used a 1Mb/s rate Feher patented FQPSK [1] Commercially Of The Shelf (COTS) product. Both hardware experimental results as well as simulation indicate substantial performance improvement with the utilization of the FE. It is demonstrated that the FE improves for a large class of frequency selective faded systems the Bit Error Rate(BER) from 10^-2 to 10^-6. Similar performance improvements are presented for the Block Error Rate (BLER).

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / FQPSK is the abbreviation for Feher Quadrature Phase Shift Keying (FQPSK) patented systems [1]. Digcom, Inc. licensed FQPSK products demonstrated significant spectral saving and RF power efficient robust BER performance advantages. These bit rate agile modems and Non Linearly Amplified (NLA) transceivers, DSP and hardware implementations, and in some instances “software-radios” (20kb/s to more than 100Mb/s) and RF frequency agile (from 150MHz to more than 40GHz) developments and systems have recently been demonstrated and deployed. The spectral efficiency, i.e., data throughput capability of the 1st generation of FQPSK, as demonstrated in initial Advanced Range Telemetry (ARTM) flight tests, approximately doubles while 2nd generation “FQPSK-2” systems have the potential to quadruple the spectral efficiency of operational PCM/FM telemetry systems and be backward compatible with the 1st generation of FQPSK technologies. It is also demonstrated that the spectral efficiency advantage of FQPSK over that of NLA power efficient GMSK, OQPSK and QPSK modulated transceivers is in the 50% to 300% range and that the potential spectral efficiency advantage of FQPSK-2 over GMSK [1] is in the 200% to 500% range. Based on extensive multi-year studies of alternative solutions for spectral and RF power efficient, robust BER performance systems, several commercial US and international organizations, AIAA, CCSDS, NASA, ESA, CCSDS and various programs of the US Department of Defense (DoD) concluded that FQPSK offers the most spectrally efficient high performance-high speed proven technology solutions and recommended FQPSK standardization for several data links. Initial DoD-ARTM Program Office Air-to-Ground L-band and S-band jet airborne telemetry Test and Evaluation (T&E) data, obtained during the summer of 1998 are briefly highlighted. These include simultaneosly tested FQPSK and PCM/FM. In these tests the following ARTM objectives have been demonstrated: (a) FQPSK approximately doubles the spectral efficiency of currently operational PCM/FM; (b) The Data Link Performance of these two systems is comparable. The American Institute of Aeronautics and Astronautics (AIAA) draft modulation standard recommended to the DoD, NASA and CCSDS, was approved by the AIAA [23]. The AIAA standard recommends “that FQPSK modulation be immediately adopted as the interim increment–1 standard.”

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / This paper presents noncoherent limiter-discriminator detection and differential detection of FQPSK (Feher quadrature phase-shift-keying) with maximum-likelihood sequence estimation (MLSE) techniques. Noncoherent FQPSK systems are suitable for fast fading and cochannel interference channels and channels with strong phase noise, and they can offer faster synchronization and reduce outage events compared with conventional coherent systems. In this paper, both differential detection and limiter-discriminator detection of FQPSK are discussed. We use MLSE with lookup tables to exploit the memory in noncoherently detected FQPSK signals and thus significantly improve the bit error rate (BER) performance in an additive white Gaussian noise (AWGN) channel.

Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The use of the quadrature mixing topology has been severely limited in the past due to its sensitivity towards mismatches between its signal paths. In recent years, researchers have suggested that digital techniques can be used to compensate for the impairments in the analogue quadrature mixing front-end. Most authors, however, focus on the modelling and compensation of frequency-independent imbalances, reasoning that this approach is sufficient for narrow band signal operation. This common assumption is, however, becoming increasing less applicable as the use of wider bandwidth signals and multi-channel systems becomes more prevalent. In this dissertation, baseband equivalent distortion models are derived, which model frequency-independent, as well as frequency-dependent contributions towards the imbalances of the front-end. Both lowpass and bandpass imbalances are modelled, which extends current modelling approaches found in literature. The resulting baseband models are shown to be capable of explaining the imbalance characteristics observed in practical quadrature mixing front ends, where existing models fail to do so. The developed imbalance models is then used to develop novel frequency-dependent imbalance extraction and compensation techniques, which directly extract the exact quadrature imbalances of the front end, using simple test tones. The imbalance extraction and compensation procedures are implemented in the digital baseband domain of the transceiver and do not require high computational complexity. The performance of these techniques are subsequently verified through simulations and a practical hardware implementation, yielding significant improvement in the image rejection capabilities of the quadrature mixing transceiver. Finally, a novel, blind imbalance compensation technique is developed. This technique is aimed at extracting frequency-independent I/Q imbalances in systems employing digital modulation schemes. No test tones are employed and the imbalances of the modulator and demodulator are extracted from the second order statistics of the received signal. Simulations are presented to investigate the performance of these techniques under various operating conditions. / AFRIKAANSE OPSOMMING: Die gebruik van die haaksfasige mengtopologie word geweldig beperk deur die sensitiwiteit vir wanbalanse wat mag bestaan tussen die twee analoog seinpaaie. In die afgelope paar jaar het navorsers digitale metodes begin voorstel om te kompenseer vir hierdie wanbalanse in die analooggebied. Meeste navorsers fokus egter op frekwensie-onafhanklike wanbalanse. Hulle staaf hierdie aanslag deur te redineer dat dit ’n aanvaarbare aaname is vir ’n nouband stelsel. Hierdie algemene aanvaarding is egter besig om minder akkuraat te raak, namate wyeband- en multikanaalstelses aan die orde van die dag raak. In hierdie tesis word basisband-ekwiwalente wanbelansmodelle afgelei wat poog om die effek van frekwensie-afhanklike en -onafhanklike wanbalanse akkuraat voor te stel. Beide laagdeurlaat- en banddeurlaatwanbalanse word gemodelleer, wat ‘n uitbreiding is op die huididge modellerings benaderings wat in literatuur gevind word. Dit word aangetoon dat die modelle van hierdie tesis daarin slaag om die karakteristieke van ’n werklike haaksfasige mengstelsel akkuraat te vervat – iets waarin huidige modelle in die literatuur nie slaag nie. Die basisband-ekwiwalente modelle word dan gebruik om nuwe digitale kompensasie metodes te ontwikkel, wat daarin slaag om die frekwensie-afhanklike wanbalanse van die haaksfasige mengstelsel af te skat, en daarvoor te kompenseer in die digitale deel van die stelsel. Hierdie kompensasiemetodes gebruik eenvoudige toetsseine om die wanbalanse af te skat. Die werksverrigting van hiedie kompensasiemetodes word dan ondersoek deur middel van simulasies en ’n praktiese hardeware-implementasie. Die resultate wys daarop dat hierdie metodes daarin slaag om ’n aansienlike verbetering in die beeldonderdrukkingsvermo¨ens van die haaksfasige mengers te weeg te bring. Laastens word daar ook ’n blinde kompensasiemetode ontwikkel, wat gemik is op frekwensie- onafhanklike wanbalanse in digital-modulasie-skama stelsels. Vir hierdie metodes is geen toetsseine nodig om die wanbalanse af te skat nie, en word dit gedoen vanuit die tweede-orde statistiek van die ontvangde sein. Die werksverrigting van hierdie tegnieke word verder bevestig deur middel van simulasies.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010. / ENGLISH ABSTRACT: This thesis describes the design and implementation of a software based QPSK demodulator with a demodulation speed of 100 Mbps. The objective of the thesis was to identify a topology for the QPSK demodulator that would allow for high data rates and the design of the synchronization algorithms for carrier and symbol recovery. The QPSK demodulator was implemented on an Altera Stratix II field programmable gate array (FPGA), which does complex I and Q sampling on a down converted 720 MHz QPSK signal. The I and Q down converted baseband signals are sent through matched filters which are implemented with discrete components to maximize the signal to noise ratio of the received rectangular baseband pulses. A 1 GSPS direct digital synthesizer (DDS) is used to generate the synchronous clock for the analog to digital converters which samples the matched filter outputs. The demodulator uses two samples per symbol to demodulate the QPSK signal. A dual locking system is implemented to have a wide pre-locking filter for symbol synchronization and a narrow band post-lock filter to minimize the loop noise. A symbol lock detection algorithm decides when the symbol recovery loop is locked and switches between the loop filters. A second 1 GSPS DDS output is mixed with a local oscillator to generate the 1.44 GHz LO signal for the quadrature down conversion. The carrier recovery loop uses a numerically controlled oscillator inside the FPGA for initial carrier acquisition which allows for very wide locking bandwidth. After lock is achieved, the external carrier recovery loop takes over and removes any frequency offset in the complex baseband signal by changing the frequency of the DDS. A QPSK modulator was also developed to provide a QPSK signal with known data. The modulator can generate any constellation diagram up to 256 points. / AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwerp en implementasie van ’n sagteware gebaseerde QPSK demodulator met ’n demodulasie spoed van 100 Mbps. Die doelstelling is om ’n topologie te identifiseer vir ’n QPSK demodulator wat ’n hoë datatempo sal toelaat en ook om sinkronisasie algoritmes te ontwikkel vir draer en simbool herkenning. Die QPSK demodulator is geïmplimenteer op ’n Stratix II FPGA van Altera wat kompleks basisband monstering doen op infase en kwadratuur basisband seine. Die basisband seine word gegenereer van ’n 720 MHz QPSK sein met ’n kwadratuur menger wiese uittrees deur puls passende filters gestuur word om die sein tot ruis verhouding te maksimeer. ’n Een gigamonster per sekonde direk digitale sintetiseerder (DDS) is gebruik om die klok vir die analoog na digitaal omsetters te genereer vir sinkrone monstering van die pulse passende filter uittrees. Die demodulator gebruik twee monsters per simbool om ’n QPSK sein te demoduleer. ’n Tweevoudige sluit algoritme word gebruik vir die simbool sinkronisasie waar ’n wyeband filter die inisiële sluit funksie verrig en dan word daar oorgeslaan na ’n nouband filter vir fase volging wat die ruis in die terugvoerlus verminder. Daar is ’n simbool sluit detektor wat identifiseer wanneer die simbool beheerlus gesluit is en selekteer dan die gepaste filter. ’n Tweede DDS en ’n sintetiseerder se uittrees word gemeng om ’n 1.44 GHz draer te genereer vir kohurente frekwensie translasie in die kwadratuur menger. Die draer sinkronisasie gebruik ’n numeries beheerbare ossilator vir die inisiële frekwensie en fase sluit wat baie vinnig geimplenteer kan word omdat dit alles in sagteware binne in die FPGA gebeur. Na die interne draer beheerlus gesluit is, neem die eksterne beheerlus oor om enige fase of frekwensie afsette in die kompleks basisband seine van die kwadratuur menger te verwyder deur die frekwensie van die draer DDS te beheer. ’n QPSK modulator is ook ontwikkel om verwysings data te genereer. Enige konstelasie vorm tot 256 punte kan geimplementeer word.