Silicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.

Silicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.

Silicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.

Este trabalho propõe novas topologias de circuitos e técnicas de projeto para filtros ativos e amplificadores de ganho programável (PGA) com operação em ultra baixa tensão (ULV) e ultra-baixa potência (ULP). Os receptores de RF do tipo Bluetooth de baixa energia (BLE), utilizados nos circuitos de internet das coisas (IoT), são as aplicações alvo dos circuitos propostos neste trabalho. Na faixa de ULV são utilizados filtros do tipo RC-ativo, uma vez que possuem uma maior linearidade em relação aos filtros do tipo gmC. A operação em ULP é alcançada neste trabalho utilizando uma nova topologia de amplificador operacional de transcondutância (OTA), com único estágio, que apresenta uma alta eficiência e reduzida sensibilidade às variações de processo, tensão e temperatura (PVT). O baixo ganho de tensão do amplificador de estágio único e os efeitos das cargas resistivas de realimentação são compensados usando um transcondutor negativo, robusto a variações em PVT, conectado às entradas do OTA. A faixa dinâmica dos circuitos é elevada usando topologias totalmente diferenciais e as taxas de rejeição de modo comum e de fonte de alimentação são melhoradas utilizando circuitos de realimentação de modo-comum. Para possibilitar a operação na faixa de ULV todos os circuitos usam apenas dois transistores empilhados e o nível de inversão do canal é elevado através da polarização direta do substrato. Neste trabalho são propostas também uma ferramenta de análise do ponto de operação do transistor, baseando-se na simulação elétrica, e algumas metodologias de projetos para circuitos operando em ULV. Os circuitos e metodologias desenvolvidos foram utilizados para o projeto de um filtro passa-faixa complexo RC-ativo de terceira ordem, um amplificador de ganho programável e um filtro biquadrático do tipo Tow-Thomas com ganho programável, compatíveis com receptores de RF do padrão BLE. Para a implementação do PGA, uma nova topologia de transconductor negativo programável foi desenvolvida para permitir a compensação ótima do amplificador operacional em todos os modos de ganho. Todos os circuitos foram projetados para operar com uma tensão de alimentação de 0,4 V e foram prototipados em processos de fabricação CMOS e BiCMOS de 180 nm e 130 nm, respectivamente. Os resultados experimentais e de simulação pós-layout demonstram uma operação adequada em 0,4 V, uma ultra-baixa dissipação de potência, atingindo o mínimo de 10.9 ?W/polo, e a melhor figura-de-mérito (FoM) em relação aos outros filtros ativos e amplificadores disponíveis na literatura. / This thesis proposes novel circuit topologies and design techniques of ultra-low voltage (ULV) and ultra-low power (ULP) active-filters and programmable gain amplifiers (PGA) suitable for the Bluetooth low energy (BLE) RF receivers used in the Internet of Things (IoT) applications. The active-RC filters are preferred to the gm-C topologies at the ULV operation due to its improved linearity. However, the closed-loop operation increases the operational amplifier required voltage gain and its capacity to drive the resistive feedback load. In this work, the ULP dissipation is obtained by proposing a very efficient single-stage inverter-based operational transconductance amplifier (OTA) and a proper forward bulk biasing to reduce the sensitivity to process, voltage and temperature (PVT) variations. The low voltage gain and the resistive load effects on the single-stage OTA are completely compensated by using a PVT robust negative transconductor connected at the OTA inputs. The dynamic range is increased by using fully-differential topologies and common-mode feedback to improve the common-mode and power supply rejection rates. The operation at the ULV range is reached by using only two-stacked transistors in all the circuit implementations and bulk forward bias in some transistors to reduce the threshold voltage and to increase the channel inversion level. An operation point simulation-based tool and some design methodologies are also proposed in this work to design the ULV circuits. The proposed circuits were used to design a third-order active-RC complex band-pass filter (CxBPF), a programmable gain amplifier (PGA) and a Tow-Thomas biquad, with integrated programmable gain capability, suitable for BLE RF receivers. The PGA implementation uses a new programmable input negative transconductor to obtain the optimal closed-loop amplifier compensation in all the gain modes. The circuits were designed to operate at the power supply voltage of 0.4 V and are prototyped in 180 nm and 130 nm low-cost CMOS and BiCMOS process, respectively. The experimental and post-layout simulation results have demonstrated the proper ULV operation at 0.4 V, the ultra-low power dissipation down to 10.9 ?W/pole and the best figure-of-merit (FoM) among the state-of-the-art active-filters and amplifiers from the literature.

Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 FranciscoAB.pdf: 846082 bytes, checksum: d9718796dd9ac807f8f053e7d371d2bb (MD5) Previous issue date: 2009-09-03 / Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico / This work presents an wideband ring VCO for cognitive radio five-port based receivers. A three-stage differential topology using transmission gate was adopted in order to maintain wide and linear tuning range and a low phase-noise. Monte-Carlo analysis were performed for phase-shift response of individual stages, which is an important figure of merit in five-port works. It was observed a fairly linear correlation between control voltage and oscillation frequency in the range between 200 MHz and 1800 MHz. The VCO was preliminarily designed for IBM 130nm CMOS technology / Este trabalho apresenta um VCO anel banda-larga para ser utilizado em receptores para R?dio Cognitivo baseados no correlator a cinco portas. Uma arquitetura diferencial de tr?s est?gios com porta de transmiss?o ? utilizada como forma de manter uma sintonia linear em larga faixa de frequ?ncias, bem como, um baixo ru?do de fase. An?lises de Monte-Carlo foram feita para avaliar as varia??es de fase em cada est?gio, o que constitui uma figura de m?rito importante em receptores baseados no correlator de cinco portas. Observou-se correspond?ncia razoavelmente linear entre tens?o de controle e freq??ncia de oscila??o na faixa compreendida entre 200 MHz e 1800 MHz. O VCO foi preliminarmente projetado para tecnologia CMOS IBM de 130 nan?metros