The scope of this thesis is to implement radar emitter emulator in a low cost, portablehardware for operational and educational purposes. The model enables pulse train generation in real environment belonging to radar emitters for military exercises. The motivation comes from another research area which is to design effective algorithms for deinterleaving mixed pulse sequences in a suitable hardware and this thesis, covers the work done for implementing a hardware that generates mixed pulse sequences. First of all, a basic radar emitter model is built up using laboratory instruments by considering basic radar emitter models. Technical specs of these instruments have to be known well to find out how many emitters can be emulated simultaneously and what the limits of these emulations are. After giving emulation results, trigging signal generator externally to obtain complex mixed pulse sequences is mentioned. In the following section related schematics are given about implementing radar emitters. Cost efficient way of emitter emulation is mentioned by using wideband RF synthesizer/VCO with integrated RF mixers and some microwave components in the following section. A board is designed including all required components to implement radar emitter emulation. Tests are implemented in laboratory environment. Finally test results and technical specifications of the design are given. Also cost calculations of the implemented designs are done in the final section and some examples related to the use of emulators in environmental scenarios are given. Future work is also explained again in this final section.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

This thesis deals with the classic and system wiring as well as their implementation and visualization environment for its operation. The aim of this work is to implement the project of the existing high-voltage and low-voltage wiring housing units accompanied by a design of the system wiring. This design is then fully implemented. In the beginning of the work is introduction to system wiring as such, added by a brief comparison of current systems. Followed by two chapters dealing with two selected systems for the realization of wiring. These chapters succinctly capture the essence of the system, its characteristics and features offered by each system. The last part deals with project design of wiring for the residential unit and the procedure for its commissioning. The practical part is dedicated to creating drawings with the existing power and low voltage distribution systems, the design of the smart wiring and electrical switchboard, together with possible modifications. The project documentation also discusses technical report. Finally, the selected system is tested and commissioned according to the requirements.

Magnetic Resonance Imaging (MRI) is an important diagnostic tool for imaging soft tissue without the use of ionizing radiation. Moreover, through advanced signal processing, MRI can provide more than just anatomical information, such as estimates of tissue-specific physical properties. Signal processing lies at the very core of the MRI process, which involves input design, information encoding, image reconstruction, and advanced filtering. Based on signal modeling and estimation, it is possible to further improve the images, reduce artifacts, mitigate noise, and obtain quantitative tissue information. In quantitative MRI, different physical quantities are estimated from a set of collected images. The optimization problems solved are typically nonlinear, and require intelligent and application-specific algorithms to avoid suboptimal local minima. This thesis presents several methods for efficiently solving different parameter estimation problems in MRI, such as multi-component T2 relaxometry, temporal phase correction of complex-valued data, and minimizing banding artifacts due to field inhomogeneity. The performance of the proposed algorithms is evaluated using both simulation and in-vivo data. The results show improvements over previous approaches, while maintaining a relatively low computational complexity. Using new and improved estimation methods enables better tissue characterization and diagnosis. Furthermore, a sequence design problem is treated, where the radio-frequency excitation is optimized to minimize image artifacts when using amplifiers of limited quality. In turn, obtaining higher fidelity images enables improved diagnosis, and can increase the estimation accuracy in quantitative MRI.

<p>Passive chipless wireless sensors have gained great attention in Radio Frequency Identification (RFID) applications, inventory tracking, and structural health monitoring, as they offer a prospective low-cost, scalable alternative to the state-of-the-art active sensors. While the popularity and demand for chipless sensors are on the rise, their applications are limited to low-noise environments and their caliber as low-cost, scalable devices has not been explored to a successful degree in challenging domains, such as precision agriculture, healthcare, and food packaging. Size, cost of materials, and complexity of the manufacturing process are the main obstacles to progress in the large-scale production of chipless sensors for practical applications. </p> <p><br></p> <p>Conventional manufacturing processes, such as photolithography, are costly, cumbersome, and time intensive. While additive manufacturing techniques, such as printing technologies, have circumvented some of these challenges, printing techniques require costly inks and complex post-processing steps, such as drying and sintering, which limit their large-scale utilization. To overcome these challenges, this dissertation focuses on investigating the possibility of utilizing laser processing of conventional metalized films and polymers to develop cost-effective chipless sensors. This Scalable Laser Assisted Manufacturing (SLAM) process offers a platform for large-scale roll-to-roll production of high-resolution sensors for precision agriculture, healthcare, and food packaging applications. </p> <p><br></p> <p>In this pursuit, the first study explores combining the SLAM process with 3D printing to develop a miniaturized, biodegradable, chipless sensor for soil moisture monitoring. In the second study, the SLAM process is further explored in the development of metalized stickers for healthcare applications focusing on urine bag management and early risk detection of urinary tract infections. In the third study, the capability of the SLAM process to form moisture-sensitive metal nanoparticles as a co-product of metal patterning is harnessed to develop a chipless humidity sensor. The SLAM process is further expanded in the fourth study by functionalizing metalized films with stimuli-responsive polymers to achieve specificity in detecting unique biomarkers of food spoilage. The SLAM platform described in this work opens up new avenues toward processing metalized fabric for the future of wearable electronics and implementing multi-functional sensors for precision agriculture.</p> <p>  </p>

<p>Пасивна индуктивна компонента и нискошумни појачавач у технологији<br />монолитних интегрисаних кола за широкопојасне примјене пројектовани<br />су, фабриковани и карактерисани. Приликом пројектовања индуктора<br />изабрана је топологија меандар, а осим софтверских алата за<br />пројектовање интегрисаних кола, кориштен је и симулатор<br />електромагнетског поља. Осим карактеризације основних параметара,<br />пажња је посвећена и анализи процесних и температурских варијација.<br />Спроведена је механичка карактеризација материјала од којег се састоји<br />заштитни слој фабрикованог интегрисаног кола. Нискошумни појачавач<br />пројектован је као први степен пријемника широкопојасне технологије, а<br />карактеризацијом је потврђена успјешност поступка.</p> / <p>Pasivna induktivna komponenta i niskošumni pojačavač u tehnologiji<br />monolitnih integrisanih kola za širokopojasne primjene projektovani<br />su, fabrikovani i karakterisani. Prilikom projektovanja induktora<br />izabrana je topologija meandar, a osim softverskih alata za<br />projektovanje integrisanih kola, korišten je i simulator<br />elektromagnetskog polja. Osim karakterizacije osnovnih parametara,<br />pažnja je posvećena i analizi procesnih i temperaturskih varijacija.<br />Sprovedena je mehanička karakterizacija materijala od kojeg se sastoji<br />zaštitni sloj fabrikovanog integrisanog kola. Niskošumni pojačavač<br />projektovan je kao prvi stepen prijemnika širokopojasne tehnologije, a<br />karakterizacijom je potvrđena uspješnost postupka.</p> / <p>A passive inductive component and a low-noise amplifier are designed,<br />fabricated in standard monolithic CMOS technology and characterized, both<br />intended for wideband operation. For the design of the inductor, meander<br />topology is chosen. Along with the integrated circuit design tools,<br />electromagnetic field simulator is used. Besides the standard parameter<br />characterization, special attention is dedicated to the analysis of process and<br />temperature variations. Furthermore, mechanical characterization of the<br />material that comprises the protection layer has been undertaken. Low-noise<br />amplifier is designed as the first stage of an ultra wideband receiver and the<br />results show that the circuit is successfully designed.</p>