<p>A new FPGA suitable for space applications has just reached the market. To investigate whether there are any possible flaws or limitations similar to those previously seen on FPGAs, an evaluation has to be done. This master thesis contains the evaluation of this new radhard FPGA with focus on possible design limitations and package related electrical phenomena.Areas evaluated: Ground-/VDD bounce, Cross talk, Rise time sensitivit, Power cycling, Power consumption, Place and route tool, Radiation hardnessThis report contains all steps in the evaluation. From method to measurements, comparisons, theory, results and conclusions. In the evaluation work, special effort has been made to develop designs that really stress the FPGA to find potential problems. All problems found are dealt with in this report.Results: Ground-/VDD bounce measurements showed that devices using a fast slew rate resulted in TTL-level violation. However, by separating sensitive signals and SSOs in different I/O banks it is possible to work around the problem. Cross talk measurements has shown that the phenomena causes problems when using a long rise time input with toggling outputs placed next to the signal. Power cycling did not result in any alarming inrush currents. Regular power up showed an unwanted behaviour with pulses on all I/Os right before power on reset kicked in. When comparing the tool value with measurements regarding power consumption it was clear that it differed as much as 40-50%. The FPGA consumes 40-50% more power than what the power calculator tool estimates.</p>

A new FPGA suitable for space applications has just reached the market. To investigate whether there are any possible flaws or limitations similar to those previously seen on FPGAs, an evaluation has to be done. This master thesis contains the evaluation of this new radhard FPGA with focus on possible design limitations and package related electrical phenomena.Areas evaluated: Ground-/VDD bounce, Cross talk, Rise time sensitivit, Power cycling, Power consumption, Place and route tool, Radiation hardnessThis report contains all steps in the evaluation. From method to measurements, comparisons, theory, results and conclusions. In the evaluation work, special effort has been made to develop designs that really stress the FPGA to find potential problems. All problems found are dealt with in this report.Results: Ground-/VDD bounce measurements showed that devices using a fast slew rate resulted in TTL-level violation. However, by separating sensitive signals and SSOs in different I/O banks it is possible to work around the problem. Cross talk measurements has shown that the phenomena causes problems when using a long rise time input with toggling outputs placed next to the signal. Power cycling did not result in any alarming inrush currents. Regular power up showed an unwanted behaviour with pulses on all I/Os right before power on reset kicked in. When comparing the tool value with measurements regarding power consumption it was clear that it differed as much as 40-50%. The FPGA consumes 40-50% more power than what the power calculator tool estimates.