In This Thesis , We primarily introduce some results with suppression of ground bounce noise in high-speed PCB by the formal researchers and summarize their advantages and weaknesses .In the next section .we explain why the EBG (Electromagnetic Band Gap ) design structure is from PBG (Photonic Band Gap ) concept in optical research field and that its principle can suppress GBN . We also summarize their advantages and weaknesses .In the following part, we define five parameters of EBG design structure to find the optimal solution by HFSS simulation method .The optimal solution can enlarge the bandwidth of suppression of GBN to 5.40GHz.We prove the accuracy of HFSS simulation method by actual measurement . When the EBG basic cell gradually compact from n=9.their characteristics are according to 1.central frequency towards high frequency 2.bandwidth of suppression of GBN is more broadband 3. forbiddance band depth becomes wider. Finally we oppose some new EBG design structures to solve some problems of old EBG design structure .These new EBG design structures can enhance signal integrity (SI) and law frequency response. Include three items 1.Meander design structure 2. Buddha design structure 3. Budder design structure .We also prove the accuracy of HFSS simulation method by actual measurement.

With electronic devices trending toward higher clock rates, lower voltage levels, and smaller form factors, the simultaneously switching noise (SSN), which is induced in package and printed circuit board, is one of the major factors affecting the performance and design of the high speed digital circuits. This noise will lead to false switching and malfunctioning in digital and/or analog circuits, and causes serious signal integrity (SI) and electromagnetic interference (EMI) problems for the high speed digital systems. Therefore, mitigating the SSN becomes a major challenge for the high speed circuits design. In this thesis, first of all, we introduce and discuss previously proposed solutions to suppress the SSN. These solutions include the use of decoupling capacitors, isolation moats, and electromagnetic bnadgap (EBG) structures. We analyzed the EBG structures and generated some EBG design rules. As the speed of digital circuits moving toward higher frequencies, the Double L-bridge EBG structure can be used to improve the performance of Hybrid EBG structure by employing the EBG design rules that were generated. The Double L-bridge EBG structure design improved the behavior at the high frequencies, which also maintained the low frequency performance. It is demonstrated numerically and experimentally. For fast estimating the stopband, we use one-dimensional lump circuit model. Then, we propose another structure, named Double Cross EBG structure. This design, compared to the Double L-bridge EBG structure, not only maintained the high frequency performance, but also improved the low frequency behavior. It is also both experimentally and numerically validated.

Transient current surges resulted from the simultaneous switching of output buffers in the high-speed digital circuits can induce significant ground bounce noise (GBN) on the chip, package, and printed circuit board (PCB). The GBN not only causes the signal integrity (SI) problems, such as glitches or timing push-out of signal traces, but also increases the electromagnetic interference (EMI) in the high-speed digital circuits. With the design trends of digital circuits toward higher speed, low voltage level, smaller volume, the impact of GBN has become one of the most important issues that determine the performance of electronic products. Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequencies higher than 600MHz due to their inherent lead inductance. Recently, a new idea for eliminating the GBN is proposed by designing electromagnetic bandgap (EBG) structure with high impedance surface (HIS) on the ground or power plane. Several new EBG power/ground plane designs have been proposed to broaden the stopband bandwidth for suppressing the GBN. However there are some drawbacks, such as high cost, large area occupation and complicated fabrication process. In this paper, we propose a novel Hybrid EBG power planes for PCB or package to suppress the GBN. Its extinctive behavior of broadband suppression of GBN (over 10GHz) is demonstrated experientially and numerically. Finally, we combine the periodic high-low dielectric material with the EBG power plane to control the position and bandwidth of stopband.

In recent high-speed digital circuits, the simultaneous switching noise (SSN) or ground bounce noise (GBN) is induced due to the transient currents flowing between power and ground planes during the state transitions of the logic gates. In order to¡@analyze the effect of GBN on power delivery systems effectively and accurately, the impedance of power/ground is an important index to evaluate power delivery systems. In the operating frequency bandwidth, the power impedance must be less than the target impedance. The typical way to suppress the SSN is adding decoupling capacitors to create a low impedance path between power and ground planes. By using the admittance matrix method, we can evaluate the effect of decoupling capacitors mounted on PCB fast and accurately reducing the time needed from the empirical or try-and-error design cycle. In order to reduce the cost of decoupling capacitors, the genetic algorithm is employed to optimize the placement of decoupling capacitors to suppress the GBN. The decoupling capacitor are not effective in the GHz frequency range due to their inherent lead inductance. The electromagnetic bandgap(EBG) structure can produce a stopband to prevent the noise from disperseing at higher frequency. Combining decoupling capacitors with EBG structure to find the optimum placement for suppression of the SSN by using the genetic algorithm.

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<p>A new FPGA suitable for space applications has just reached the market. To investigate whether there are any possible flaws or limitations similar to those previously seen on FPGAs, an evaluation has to be done. This master thesis contains the evaluation of this new radhard FPGA with focus on possible design limitations and package related electrical phenomena.Areas evaluated: Ground-/VDD bounce, Cross talk, Rise time sensitivit, Power cycling, Power consumption, Place and route tool, Radiation hardnessThis report contains all steps in the evaluation. From method to measurements, comparisons, theory, results and conclusions. In the evaluation work, special effort has been made to develop designs that really stress the FPGA to find potential problems. All problems found are dealt with in this report.Results: Ground-/VDD bounce measurements showed that devices using a fast slew rate resulted in TTL-level violation. However, by separating sensitive signals and SSOs in different I/O banks it is possible to work around the problem. Cross talk measurements has shown that the phenomena causes problems when using a long rise time input with toggling outputs placed next to the signal. Power cycling did not result in any alarming inrush currents. Regular power up showed an unwanted behaviour with pulses on all I/Os right before power on reset kicked in. When comparing the tool value with measurements regarding power consumption it was clear that it differed as much as 40-50%. The FPGA consumes 40-50% more power than what the power calculator tool estimates.</p>

A new FPGA suitable for space applications has just reached the market. To investigate whether there are any possible flaws or limitations similar to those previously seen on FPGAs, an evaluation has to be done. This master thesis contains the evaluation of this new radhard FPGA with focus on possible design limitations and package related electrical phenomena.Areas evaluated: Ground-/VDD bounce, Cross talk, Rise time sensitivit, Power cycling, Power consumption, Place and route tool, Radiation hardnessThis report contains all steps in the evaluation. From method to measurements, comparisons, theory, results and conclusions. In the evaluation work, special effort has been made to develop designs that really stress the FPGA to find potential problems. All problems found are dealt with in this report.Results: Ground-/VDD bounce measurements showed that devices using a fast slew rate resulted in TTL-level violation. However, by separating sensitive signals and SSOs in different I/O banks it is possible to work around the problem. Cross talk measurements has shown that the phenomena causes problems when using a long rise time input with toggling outputs placed next to the signal. Power cycling did not result in any alarming inrush currents. Regular power up showed an unwanted behaviour with pulses on all I/Os right before power on reset kicked in. When comparing the tool value with measurements regarding power consumption it was clear that it differed as much as 40-50%. The FPGA consumes 40-50% more power than what the power calculator tool estimates.

In recent high-speed digital circuits with pico-second rising/falling edges, it is reasonable to consider the power/ground planes as a dynamic electromagnetic system. The simultaneous switching noise (SSN) or ground bounce noise (GBN), resulting from the transient currents which flow between power/ground planes during the state transitions of the logic gates, has become a critical factor to degrade the signal integrity (SI) and power integrity (PI) in PCB or package design. In order to accurately perform overall system-level power integrity simulation, extracting the SPICE-compatible models with the resonant effect being considered in the power/ground planes and incorporating the model into the conventional circuit simulator, such as SPICE, is essential. In this thesis, a two-dimensional transmission line (2D-TL) model is proposed for constructing the SPICE-compatible model of the power/ground planes. Based on this model, the ground bounce noise for the BGA package mounted on a PCB can be efficiently evaluated. It is found that the behavior of GBN between the only package and package mounted on a PCB (hybrid structure) is obvious different. Then, we combine the SPICE-compatible model of the power/ground planes with decoupling capacitors to fast evaluate the behavior of GBN. It also has a good agreement between our model and the measured result. Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequency higher than GHz due to their inherent lead inductance. In recent, a new method for eliminating the GBN at higher frequency is proposed by electromagnetic bandgap (EBG) structure with high impedance surface (HIS). Finally, we utilize 2D-TL model to fast analyze the behavior of the EBG, and combine decoupling capacitors with EBG structure to research the suppression of the GBN.

In this thesis, we study the electromagnetic effect of the high-speed digital PCB in three sections. In first section, based on the FDTD modeling approach, the bridging effect of the isolation moat on the EMI caused by the ground bounce noise is investigated. We find that isolating the noise source by slits is effective to eliminate the EMI, but bridges connecting between two sides of the slits will significantly degrade the effect of EMI protection. In second section, we investigate both in time and frequency domains the power plane noise coupling to signal trace with via transition in multi-layered PCB. Separating the power plane with slits is effective in reducing noise coupling in high frequency but a new resonant mode will be excited at lower frequency. Current distribution pattern of this new resonant mode between the power planes helps us to understand this phenomenon more clearly. In final section, by using FDTD link SPICE method, we can predict the electromagnetic behavior of the PCB with active device effectively.

The operation speed of modern computer system has been upgraded from several hundred MHz to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power and ground plane, so called ¡§Ground bounce.¡¨ To prevent the ground bounce from IC operation, decoupling capacitors are used. In this thesis, an efficient numerical approach which is based on the two-dimensional (2D) finite-difference time-domain (FDTD) method and with a new recursive algorithm has been used for modeling the power/ground planes characteristics with SMT capacitors above them. By the way, we take several methods, such as Debye model, FDTD-SPICE, and telegrapher¡¦s equation, for modeling various mother board structures. Finally, we use the genetic algorithm for calculating the optimum capacitor placements to meet the expect ground bounce limitation.