The focus of this work is on the steady-state analysis of RE circuits using a coupled device and circuit simulator. Efficient coupling algorithms for both the time-domain shooting method and the frequency-domain harmonic balance method have been developed. A modified Newton shooting method considerably improves the efficiency and reliability of the time-domain analysis. Three different implementation approaches of the harmonic balance method for coupled device and circuit simulation are investigated and implemented. These include the quasi-static, non-quasi-static, and modified-Volterra-series approaches. Comparisons of simulation and performance results identify the strengths and weakness of these approaches in terms of accuracy and efficiency. / Graduation date: 2005

Tang Siu Kei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 107-111). / Abstracts in English and Chinese. / Acknowledgements --- p.ii / Abstract --- p.iii / List of Figures --- p.xi / List of Tables --- p.xvi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1 / Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1 / Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4 / Chapter 1.3 --- Research Goal and Contribution --- p.6 / Chapter 1.4 --- Thesis Outline --- p.6 / Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8 / Chapter 2.1 --- Amplifier Gain --- p.8 / Chapter 2.2 --- Noise Factor --- p.9 / Chapter 2.3 --- Linearity --- p.11 / Chapter 2.3.1 --- 1-dB Compression Point --- p.13 / Chapter 2.3.2 --- Third-Order Intercept Point --- p.14 / Chapter 2.4 --- Return Loss --- p.16 / Chapter 2.5 --- Power Consumption --- p.18 / Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19 / Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21 / Chapter 3.1 --- Dual-Diode Circuitry --- p.22 / Chapter 3.1.1 --- Working Principle --- p.22 / Chapter 3.1.2 --- Drawbacks --- p.24 / Chapter 3.2 --- Shunt-Inductor Method --- p.25 / Chapter 3.2.1 --- Working Principle --- p.25 / Chapter 3.2.2 --- Drawbacks --- p.27 / Chapter 3.3 --- Common-Gate Input Stage Method --- p.28 / Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29 / Chapter 3.3.2 --- Competitiveness --- p.31 / Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32 / Chapter 4.1 --- Small-Signal Modeling --- p.33 / Chapter 4.2 --- Method of Input Termination --- p.33 / Chapter 4.2.1 --- Resistive Termination --- p.34 / Chapter 4.2.2 --- Shunt-Series Feedback --- p.34 / Chapter 4.2.3 --- l/gm Termination --- p.35 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.36 / Chapter 4.3 --- Method of Gain Enhancement --- p.38 / Chapter 4.3.1 --- Tuned Amplifier --- p.38 / Chapter 4.3.2 --- Multistage Amplifier --- p.40 / Chapter 4.4 --- Improvement of Reverse Isolation --- p.41 / Chapter 4.4.1 --- Common-Gate Amplifier --- p.41 / Chapter 4.4.2 --- Cascoded Amplifier --- p.42 / Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44 / Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44 / Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46 / Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49 / Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49 / Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52 / Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54 / Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55 / Chapter 6.2 --- Design of Two-Stage Architecture --- p.57 / Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57 / Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59 / Chapter 6.3 --- Stability Consideration --- p.61 / Chapter 6.4 --- Design of Matching Networks --- p.62 / Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64 / Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67 / Chapter Chapter 7 --- Layout Considerations --- p.70 / Chapter 7.1 --- MOS Transistor --- p.70 / Chapter 7.2 --- Capacitor --- p.72 / Chapter 7.3 --- Spiral Inductor --- p.74 / Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76 / Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79 / Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81 / Chapter Chapter 8 --- Measurement Results --- p.82 / Chapter 8.1 --- Experimental Setup --- p.82 / Chapter 8.1.1 --- Testing Circuit Board --- p.83 / Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84 / Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84 / Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85 / Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86 / Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87 / Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89 / Chapter 8.2.1 --- S-parameter Measurement --- p.90 / Chapter 8.2.2 --- Noise Figure Measurement --- p.91 / Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92 / Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93 / Chapter 8.2.5 --- HBM ESD Test --- p.94 / Chapter 8.2.6 --- Summary of Measurement Results --- p.95 / Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96 / Chapter 8.3.1 --- s-parameter Measurement --- p.97 / Chapter 8.3.2 --- Noise Figure Measurement --- p.98 / Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99 / Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100 / Chapter 8.3.5 --- HBM ESD Test --- p.101 / Chapter 8.3.6 --- Summary of Measurement Results --- p.102 / Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103 / Chapter Chapter 9 --- Conclusion and Future Work --- p.105 / Chapter 9.1 --- Conclusion --- p.105 / Chapter 9.2 --- Future Work --- p.106 / References --- p.107 / Author's Publications --- p.112

Chan, Chi Fat. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.2 / 摘要 --- p.5 / Acknowledgement --- p.7 / Table of Contents --- p.9 / List of Figures --- p.11 / List of Tables --- p.14 / Chapter 1. --- Introduction --- p.15 / Chapter 1.2. --- Research Objectives --- p.16 / Chapter 1.3. --- Thesis Organization --- p.18 / Chapter 1.4. --- References --- p.19 / Chapter 2. --- Overview of Passive UHF RFID Transponders --- p.20 / Chapter 2.1. --- Types of RFID Transponders and Design Challenges of Passive RFID Transponder --- p.20 / Chapter 2.2. --- Selection of Carrier Frequency --- p.22 / Chapter 2.3. --- Description of Transponder Construction --- p.22 / Chapter 2.3.1. --- Power-Generating Circuits --- p.23 / Chapter 2.3.2. --- Base Band Processor --- p.28 / Chapter 2.3.3. --- Signal Front-End --- p.29 / Chapter 2.4. --- Summary --- p.30 / Chapter 2.5. --- References --- p.31 / Chapter 3. --- ASK Demodulator for EPC C-l G-2 Transponder --- p.32 / Chapter 3.1. --- ASK Demodulator Design Considerations --- p.32 / Chapter 3.1.1. --- Recovered Envelope Distortion --- p.32 / Chapter 3.1.2. --- Input Power Level Considerations --- p.34 / Chapter 3.1.3. --- Input RF power Intercepted by ASK Demodulator --- p.36 / Chapter 3.2. --- ASK Demodulator Design From [3-4] --- p.36 / Chapter 3.2.1. --- Envelope Waveform Recovery Design --- p.37 / Chapter 3.2.1.1. --- Voltage Multiplier Branch for Generating Venv --- p.39 / Chapter 3.2.1.2. --- Voltage Multiplier Branch for Generating Vref --- p.41 / Chapter 3.2.2. --- Design Considerations for Sensitivity of ASK Demodulator --- p.41 / Chapter 3.2.3. --- RF Input Power Sharing with Voltage Multiplier --- p.44 / Chapter 3.2.4. --- ASK Demodulator and Voltage Multiplier Integrated Estimations for Maximum RF Power Input --- p.47 / Chapter 3.2.5. --- Measurement result and Discussion --- p.49 / Chapter 3.3. --- Proposed Envelope Detector Circuit --- p.52 / Chapter 3.3.1. --- Sensitivity Estimation --- p.52 / Chapter 3.3.2. --- Maximum Tolerable Input Power Estimation --- p.53 / Chapter 3.3.3. --- Envelope Waveform Recovery of the Proposed Envelope Detector --- p.54 / Chapter 3.4. --- Summary --- p.57 / Chapter 3.5. --- References --- p.58 / Chapter 4. --- Clock Generator for EPC C-l G-2 Transponder --- p.59 / Chapter 4.1. --- Design Challenges Overview of Clock Generator --- p.59 / Chapter 4.2. --- Brief Review of PIE Symbols in EPC C1G2 Standard --- p.62 / Chapter 4.3. --- Proposed Clock Recovery Circuit Based on PIE Symbols for Clock Frequency Calibration --- p.64 / Chapter 4.3.1. --- Illustration on PIE Symbols for Clock Frequency Calibration --- p.64 / Chapter 4.3.2. --- Symbol time-length counter --- p.72 / Chapter 4.3.3. --- The M2.56MHZ Reference Generator and Sampling Frequency Requirement --- p.75 / Chapter 4.3.4. --- Symbol Length Reconfiguration for Different Tari and FLL Stability --- p.80 / Chapter 4.3.5. --- Frequency Detector and Loop Filter --- p.83 / Chapter 4.3.6. --- Proposed DCO Design --- p.84 / Chapter 4.3.7. --- Measurement Results and Discussions --- p.88 / Chapter 4.3.7.1. --- Frequency Calibration Measurement Results --- p.89 / Chapter 4.3.7.2. --- Number x and Tari Variation --- p.92 / Chapter 4.3.7.3. --- Temperature and Supply Variation --- p.93 / Chapter 4.3.7.4. --- Transient Supply Variation --- p.94 / Chapter 4.3.8. --- Works Comparison --- p.95 / Chapter 4.4. --- Clock Generator with Embedded PIE Decoder --- p.96 / Chapter 4.4.1. --- Clock Generator for Transponder Review --- p.96 / Chapter 4.4.2. --- PIE Decoder Review --- p.97 / Chapter 4.4.3. --- Proposed Clock Generator with Embedded PIE Decoder --- p.97 / Chapter 4.4.4. --- Measurement Results and Discussions --- p.100 / Chapter 4.5. --- Summary --- p.103 / Chapter 4.6. --- References --- p.105 / Chapter 5. --- ASK Modulator --- p.107 / Chapter 5.1. --- Introduction to ASK Modulator in RFD Transponder --- p.107 / Chapter 5.2. --- ASK Modulator Design --- p.109 / Chapter 5.3. --- ASK Modulator Measurement --- p.110 / Chapter 5.4. --- Summary --- p.113 / Chapter 5.5. --- References --- p.113 / Chapter 6. --- Conclusions --- p.114 / Chapter 6.1. --- Contribution --- p.114 / Chapter 6.2. --- Future Development --- p.116

A new comprehensive wide-band compact modeling methodology for single-ended spiral inductors and differential spiral inductors is presented. The new modeling methodology creates an equivalent circuit model consisting of frequency-independent circuit elements for use in circuit simulators. A fast automated extraction procedure is developed for determining the circuit element values from two-port S-parameter measurement data. The methodology is extremely flexible in allowing for accurate modeling of general classes of inductors on high or low resistivity substrate and for large spirals exhibiting distributed trends. The new modeling methodology is applied to general classes of spirals with various sizes and substrate parameters. The presented compact modeling methodology has major benefits including greatly reducing model extraction time in comparison with currently available models based on optimization methods. To demonstrate the accuracy in comparison with past models a number of measurement data sets are used for sample extractions. A developed computer program is presented and used for circuit model extractions. Results are presented when the computer program is applied to a high-volume inductor extraction. The extracted models show excellent agreement with the measured data sets over the frequency range of 0.1 to 10 GHz. / Graduation date: 2004

Thesis (Ph. D.)--University of Nevada, Reno, 2005. / "December 2005." Includes bibliographical references (leaves 213-220). Online version available on the World Wide Web. Library also has microfilm. Ann Arbor, Mich. : ProQuest Information and Learning Company, [2005]. 1 microfilm reel ; 35 mm.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Madhaven Swaminathan. / Vita. Includes bibliographical references (leaves 154-163).

Thesis (Ph. D.)--Ohio State University, 2007. / Full text release at OhioLINK's ETD Center delayed at author's request

Thesis (Ph. D.)--Auburn University. / Abstract. Vita. Includes bibliographical references (p. 160-167).

Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2008. / Includes bibliography (p. 165-171) Also available in print form.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 79-81). Also available in electronic format on the Internet.