Wireless communication circuits rely on the use of high-quality passive elements (inductor-capacitor resonant tanks) for the implementation of selective filters and high-purity frequency references (oscillators). Typically available CMOS, on-chip passives suffer from high losses, primarily inductors, and consume large areas that cannot be populated by transistors leading to a significant area penalty. Mechanical resonators exhibit significantly lower losses than their electrical counterparts due to the reduced parasitic loss mechanisms in the mechanical domain. Efficient transduction schemes such as the piezoelectric effect allow for simple electrical actuation and read-out of such mechanical resonators. Piezoelectric thin-film bulk acoustic resonators (FBARs) are currently among the most promising and widely used mechanical resonator structures. However, FBARs are currently only available as off-chip components, which must be connected to CMOS circuitry through wire-bonding and flip-chip schemes. The use of off-chip interfaces introduces considerable parasitics and significant limitations on integration density. Monolithic integration with CMOS substrates alleviates interconnect parasitics, increases integration density and allows for area sharing whereby FBARs reside atop active CMOS circuitry. Close integration of FBARs and CMOS transistors can also enable new circuit paradigms, which simultaneously leverage the strengths of both components. Described here, is a body of work conducted to integrate FBAR resonators with active CMOS substrates (180nm and 65nm processes). A monolithic fabrication method is described which allows for FBAR devices to be constructed atop the backend small CMOS dies through low thermal-budget (< 300°C) post-processing. Stand-alone fabricated devices are characterized and the extracted electrical model is used to design two oscillator chips. The chips comprise amplifier circuitry that functions along with the integrated FBARs to achieve oscillation in the 0.8-2 GHz range. The chips also include test structures to assess the performance of the underlying CMOS transistors before and after the resonator post-processing. A successful FBAR-CMOS oscillator is demonstrated in 65nm CMOS along with characterization of FBARs built on CMOS. The approach presented here can be used for experimenting with more complex circuits leveraging the co-integration of piezoelectric resonators and CMOS transistors.

米勒補償是現今最被廣泛使用的頻率補償方法之一。其極點分離現象為雙級放大器供簡易而又可靠的穏定作用。可是，隨着亞微米 CMOS 技術及低電壓電路設計的興起，高增益同時又寬頻寬的放大器設計變得愈來愈困難。雖然多階段方式能實現高增益的放大器規格，但其頻寬會隨之縮窄，頻率補償亦會變得複雜及困難。 / 在過去，很多學術硏究報告都提出了不少方法去解決多階段放大器頻寬縮窄的問題，但這些方法往往離開複雜的頻率補償技巧及電路結構。為了根本性地解決此問題，本論文會提出一個虛擬雙階段放大器的設計。此放大器設計利用了兩個低增益階段來放大進入第二階段前的訊號振幅，從而放進整個放大器的頻寬及增益。由於其簡單的結構，這個設計仍然能夠採用穏定可靠的簡易米勒補償方式來穏定整個放大器。 / 這個設計由CMOS 180nm（互補式屬-氧化層-半導體180納米）技術製成。實驗結果證實了其高增益及寬頻寬的效能。另外，這果放大器亦同時應用在一個低通濾波器的實現上，用以證明其實際應用上的用途。實驗結果證實利用該放大器實現的低通濾波器比用一般雙段放大器的功率消耗減少近 45%。 / Miller compensation is one of the most widely adopted frequency compensation techniques for two-stage amplifier design. With its pole-splitting behavior achieved by connecting a capacitor between the output nodes of the two gain stages, Miller compensation provides a simple and reliable stabilizing function to two stage amplifiers. However, with the advance of sub-micron CMOS technology and low-voltage circuit designs, high-gain and wide-bandwidth amplifier design becomes more difficult. Although multi-stage amplifiers can be used to attain high-gain specification, the bandwidth will be degraded dramatically and the frequency compensation scheme becomes much more complicated. / To solve the problem, several researches have been done to improve the frequency response of multi-stage amplifiers so as to achieve high-gain and wide-bandwidth specifications simultaneously. However, these always result in the increase of circuit complexity and more complicated frequency compensation techniques. / In this thesis, a virtual two-stage Miller compensated amplifier will be proposed. By using two small gain stages, the characteristics of a conventional two-stage Miller compensated amplifier can be retained due to the low output impedance of the two gain stages. The small gain stages boost the input signal amplitude of the second stage such that the generated small-signal output current can be increased significantly. This results in wider signal bandwidth and higher voltage gain. / The proposed design has been fabricated in UMC CMOS 0.18μm technology. Experimental results have verified the concept. From the measurement, the unity-gain frequency of the proposed design is better than the conventional design by 4 times. Moreover, the voltage gain is improved by about 20dB. The current consumption is 124.76μA which is the nearly the same as the conventional design. / In order to show the improvement in real applications, the proposed amplifier has been applied to a fifth-order low-pass filter with corner frequency of 50kHz. Under the same performance, the power consumption of the filter using the proposed amplifier can be reduced by about 45%. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Poon, Hiu Ching. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgments --- p.iv / Table of Content --- p.v / List of Figures --- p.vii / List of Tables --- p.xi / Symbols Declarations --- p.xii / Chapter Chapter 1 --- Background Information / Chapter 1.1 --- High-Gain Amplifier and its Application with Negative Feedback Configuration --- p.1-1 / Chapter 1.2 --- High-Gain Amplifier Design and the Tradeoffs --- p.1-6 / Chapter 1.3 --- High-Gain Amplifier Implementations --- p.1-8 / Chapter 1.4 --- Contribution and Outlines of the Thesis --- p.1-15 / References --- p.1-16 / Chapter Chapter 2 --- Analysis of Frequency Compensation Techniques / Chapter 2.1 --- Simple Miller Compensation --- p.2-1 / Chapter 2.2 --- Miller Compensation with Null Resistor --- p.2-10 / Chapter 2.3 --- Miller Compensation with Multipath Zero Cancellation --- p.2-13 / Chapter 2.4 --- Nested Miller Compensation --- p.2-15 / Chapter 2.5 --- Advanced Frequency Compensation Techniques --- p.2-17 / Chapter 2.6 --- Conclusion of Chapter --- p.2-20 / References --- p.2-22 / Chapter Chapter 3 --- Proposed Amplifier Design / Chapter 3.1 --- Gain Tolerance --- p.3-1 / Chapter 3.2 --- Adjustments on Simple Miller Compensated Two-Stage Amplifier --- p.3-3 / Chapter 3.3 --- Introducing the Small Gain Stage --- p.3-4 / Chapter 3.4 --- Concept of the Proposed Virtual Two-Stage Miller Compensated Amplifier --- p.3-7 / Chapter 3.5 --- Comparisons with Bandwidth Enhanced Miller Compensated Two-Stage Amplifier --- p.3-9 / Chapter 3.6 --- Proposed Virtual Two-Stage Amplifier with Simple Miller Compensation --- p.3-13 / Chapter 3.7 --- Design Considerations and Expected Performance --- p.3-15 / Chapter 3.8 --- Experimental Result --- p.3-18 / Chapter 3.9 --- Conclusions of Chapter --- p.3-31 / References --- p.3-32 / Chapter Chapter 4 --- Implementation of the Low-Pass Filter / Chapter 4.1 --- Implementation of the Low-Pass Filter --- p.4-1 / Chapter 4.2 --- Experimental Result --- p.4-4 / Chapter 4.3 --- Conclusion of Chapter --- p.4-7 / Reference --- p.4-8 / Chapter Chapter 5 --- Conclusion and Future Work / Chapter 5.1 --- Conclusion of Thesis --- p.5-1 / Chapter 5.2 --- Suggestion for Future Work --- p.5-2

However, the proposed receiver and channel selection scheme still suffer from the mismatches picked up during RF-to-IF conversion. Therefore, a system called phase and amplitude mismatch cancellers is adopted to deal with the problem. Existing implementations neglected several critical behaviors of the cancellers, and provide image rejection ratios (IRR) ranging from 50dB to 65dB only. These behaviors include (i) arithmetic underflow, (ii) angular obscurity and (iii) spurious intermodulation products (IMD) produced by cancellers. We analyzed them and established several design rules, by which a far better IRR of at least 82.5dB was achieved. The system makes the proposed receiver and channel selection method feasible. / In traditional receivers involving intermediate frequency (IF), two different RF channels, Signal and Image, are converted to the same IF and overlap with each other. The Signal is always wanted with the Image eliminated, so each RF LO frequency can only select one RF channel. By digital low-IF, the IF-to-baseband conversion can be configured so that either channel can be selected, then each RF LO frequency can select two RF channels. This enhanced channel selection scheme can effectively reduce the number of LO frequency locations by half as well as the requirements of RF PLL frequency synthesizer. An existing approach makes use of configurable sampling scheme to achieve the same aim, but its use of analog sampling circuits results in phase and amplitude mismatches, from which the performance of image rejection suffers. Digital low-IF does not have this problem, since no mismatches are introduced to the signals after digitization. / The proposed digital low-IF Weaver receiver, together with the enhanced channel selection scheme and the phase and amplitude mismatch cancellers, are demonstrated to be feasible by a multi-band multi-mode receiver prototype supporting GSM900 and WCDMA. / The receiver architecture proposed in this thesis makes use of Weaver architecture with digital low-IF. Its flexibility allows for any operations to be performed on the digitized signals, as well as the enhanced channel selection scheme proposed in this thesis. / Chan Pak Kee. / "September 2007." / Adviser: Chiu Sing Choy. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4924. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 152-162). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Au-Yeung Chung-Fai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 85-91). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Contents --- p.iv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Basic Theory of Mixer --- p.6 / Chapter 2.1 --- Definition of mixer's electrical parameters --- p.8 / Chapter 2.2.1 --- Conversion gain --- p.8 / Chapter 2.2.2 --- Port-to-port isolation --- p.8 / Chapter 2.2.3 --- Noise figure --- p.9 / Chapter 2.2.4 --- 1-dB compression point (P1dB) --- p.11 / Chapter 2.2.5 --- 2nd order intercept point (IP2) --- p.11 / Chapter 2.2.6 --- 3rd order intercept point (IP3) --- p.12 / Chapter 2.2.7 --- Blocking dynamic range (BDR) --- p.12 / Chapter 2.2.8 --- Spurious free dynamic range (SFDR) --- p.12 / Chapter 2.2 --- Review of mixer architectures --- p.13 / Chapter 2.2.1 --- Diode mixer --- p.13 / Chapter 2.2.2 --- Dual-gate mxer --- p.14 / Chapter 2.2.3 --- Singly balanced mixer --- p.15 / Chapter 2.2.4 --- Doubly balanced dual-gate mixer --- p.16 / Chapter 2.2.5 --- Gilbert cell mixer --- p.18 / Chapter Chapter 3 --- CMOS Doubly Balanced Dual-Gate Mixer Design --- p.20 / Chapter 3.1 --- Design and Analysis --- p.20 / Chapter 3.1.1 --- Principle of operation --- p.20 / Chapter 3.1.2 --- Doubly balanced dual-gate mixer --- p.23 / Chapter 3.1.3 --- Common source output buffer --- p.25 / Chapter 3.1.4 --- Design example and simulation results --- p.26 / Chapter 3.2 --- IC Layout --- p.29 / Chapter 3.2.1 --- Multi-fingers transistor --- p.29 / Chapter 3.2.2 --- Matched transistor --- p.31 / Chapter 3.2.3 --- Match resistor --- p.32 / Chapter 3.2.4 --- Layout of CMOS doubly balanced dual-gate mixer --- p.33 / Chapter Chapter 4 --- Review of Mixer Linearization Techniques --- p.34 / Chapter 4.1 --- Source degeneration --- p.34 / Chapter 4.2 --- Feed-forward system --- p.36 / Chapter 4.3 --- Predistortion --- p.38 / Chapter 4.4 --- Difference-frequency (low-frequency) injection technique --- p.41 / Chapter Chapter 5 --- Mixer Linearization 一 Low Frequency Signal Injection --- p.44 / Chapter 5.1 --- Mixer's linearity --- p.44 / Chapter 5.2 --- Low-frequency signal injection method --- p.46 / Chapter 5.2.1 --- Single-injection scheme --- p.49 / Chapter 5.2.2 --- Dual-injection scheme --- p.50 / Chapter 5.2.3 --- Effect of gain error --- p.51 / Chapter 5.2.4 --- Bandwidth lim itation --- p.52 / Chapter Chapter 6 --- Experiments and Results --- p.55 / Chapter 6.1 --- CMOS doubly balanced dual-gate mixer --- p.55 / Chapter 6.1.1 --- Conversion gain --- p.56 / Chapter 6.1.2 --- Port-to-port isolation --- p.57 / Chapter 6.1.3 --- No ise figure --- p.60 / Chapter 6.1.4 --- 1-dB compression point --- p.61 / Chapter 6.1.5 --- 3rd order intercept point --- p.62 / Chapter 6.2 --- Low-frequency signal injection method --- p.63 / Chapter 6.2.1 --- Measurement result: single-injection scheme --- p.64 / Chapter 6.2.2 --- Measurement result: dual-injection scheme --- p.66 / Chapter Chapter 7 --- Conclusions and Recommendations for Future Work --- p.68 / Chapter 7.1 --- Conclusions --- p.68 / Chapter 7.2 --- Recommendations for future work --- p.69 / Appendix --- p.70 / Chapter A1 --- CMOS technology --- p.70 / Chapter A1.1 --- MOSFET structure --- p.70 / Chapter A1.2 --- CMOS n-well process --- p.71 / Chapter A1.3 --- MOSFET device modeling --- p.74 / Chapter A1.4 --- Channel length modulation --- p.78 / Chapter A1.5 --- Body effect --- p.78 / Chapter A2 --- Mixer's nonlinearity analysis --- p.79 / Chapter A2.1 --- First-order effect --- p.79 / Chapter A2.2 --- Second-order effect --- p.80 / Chapter A2.3 --- Third-order effect --- p.81 / Chapter A2.4 --- Nonlinear IF spectrum --- p.82 / Chapter A3 --- Artificial IMD3 produced by low-frequency signal injection --- p.83 / Author's Publication List --- p.85 / References --- p.86

Wireless communication technologies are no longer limited for voice band applications, but have entered the era for multimedia data link. The IEEE802.11 family, which occupies a bandwidth in the multi-mega hertz region with the highest data rate of 54 Mbps, now has become the most widely deployed wireless LAN standards. The rapid adoption of IEEE802.11 for computer wireless networks and their growing popularity in mobile applications highlight the need for a low cost, low power consumption, and monolithic solution. To meet this challenge, traditional RF techniques, which revolved around the superheterodyne architecture can no longer be used. On the contrary, new receiver frontend architectures need to be developed to satisfy the demand of system level integration. Direct downconversion receivers directly translate the RF spectrum to the baseband by setting the LO frequency equal to the RF. Due to the single frequency translation, expensive and bulky off-chip filters and 50 ohm I/O matching networks at IF are no longer required. Also, the single-stage quadrature mixers further simplify the receiver design and reduce the power dissipation. Subsequent baseband components and ADCs are also possible to be integrated with the RF frontend to achieve a monolithic receiver chip. Despite the previously mentioned advantages, the implementation of a direct downconversion receiver has its own set of performance challenges. In particular, the performance is plagued by DC offset, flicker noise, linearity and mismatches etc. The main objective of this project is to investigate the feasibility of using direct downconversion architecture for the IEEE802.11a standard, and implement the design in a 0.18 µm CMOS technology. By approaching the design issue at a theoretic point of view, extensive modeling and simulations based on a SIMULINK IEEE802.11a physical layer theme have been carried out to evaluate the receiver performance. SER results of the receiver demonstrate that the impairments associated with zero IF can be minimised to an acceptable level. Under the guidance of the system level analysis, the circuit level design of a monolithic direct downconversion receiver has been implemented in a 0.18 µm RF CMOS process, including the building blocks of an LNA, mixer, baseband amplifier and a channel-selection filter. Particularly, a novel LNA design methodology with an improved noise figure and less power consumption has been developed. The mixer conversion gain and phase noise have been analysed by a novel approach. The combination topology of the highpass DC offset removal filter and the baseband amplifier provids the best linearity with a negligible noise figure degradation. Circuit simulations are performed using the foundry provided RF design kit with enhanced noise models to capture the extra noise of passive and deep submicron devices. Circuit level simulations show a qualified receiver frontend for the IEEE802.11a standard. As data converters are important building blocks in wireless receivers, research on high performance Sigma-Delta modulators is also included. MATLAB based programs have been developed for both the discrete and continuous time transfer function synthesis. A BPSDM chip with variable centre frequencies has been developed to verify the SDM transfer function algorithm and the design methodology. The design of an ultra fast continuous time SDM is particularly focused on for a broadband data conversion. To alleviate the challenge of the comparator speed limit, a novel noise transfer function with a unit clock delay has been synthesised. With such a delayed transfer function, a three-stage comparator can be acheieved that solves the comparator gain and speed tradeoff. The full chip simulation shows an acceptable performance for the IEEE802.11a standard. / Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2008

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 158-164).

The objective of this thesis is to design RF circuits using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for communication system. The packaging effect for the SiGe chip using liquid crystal polymer (LCP) is presented and methodology to derive the model for the package is discussed. Chapter 1, we discuss the overview and benefits of SiGe HBT technology in high frequency circuit design. Chapter 2 presents the methodology of the low noise amplifier (LNA) design and discusses the trade-off between the noise and gain matching. The technique for achieving simultaneous noise and gain matching for the LNA is also presented. Chapter 3 presents an L-band cascaded feedback SiGe low noise amplifier (LNA) design for use in Global Position System (GPS) receivers. Implemented in a 200 GHz SiGe BiCMOS technology, the LNA occupies 1 x 1 millimeter square (including the bondpads). The SiGe LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1-dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of -3.98 dBm. Lastly, Chapter 4 covers the packaging techniques for the SiGe monolithic integrated circuit (MMIC). We present the modeling of a liquid crystal polymer (LCP) package for use with an X-band SiGe HBT Low Noise Amplifier (LNA). The package consists of a 2 mil LCP laminated over an embedded SiGe LNA, with vias in the LCP serving as interconnects to the LNA bondpads. An accurate model for the packaging interconnects has been developed and verified by comparing to measurement results, and can be used in chip/package co-design.

The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion of an RF combiner. It is newly proposed that two distinct digital predistortion algorithms are required for perfect compensation for both PAs and a combiner. All phase calibration values can be adaptively calculated as a function of outphase angle and saved in digital look-up tables to predistort the phase inputs of two DPMs. Various types of PAs and combiners are investigated to further enhance the performance of the outphasing transmitter. These features are implemented in a chip fabricated in a 0.18-¥ìm CMOS process and evaluated with IEEE 802.16e baseband symbols.

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (p. 163-176).

Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 102-109).