Algorithms and simulators comprised of SPICE3 as a circuit level simulator and two device simulators EOFLOW and PROPHET for accurate simulation of new types of devices are presented in this thesis. An integration of EOFLOW with SPICE3 creates a capability for efficient simulation of a system containing interconnected electroosmotic flow channels together with control electronics. Using this simulator, an accurate simulation of a complex interconnection of channels has been performed. In addition, various flow control schemes have been evaluated for their effectiveness. Coupling of PROPHET and SPTCE3 allows for the simulation of accurate semiconductor device models. This capability is necessary for critical RF and analog applications. The coupled SPICE3-HB-PROPHET simulator incorporates the harmonic balance algorithm for large-signal frequency domain analysis. Applications of this analysis are demonstrated in the noise coupling between devices sharing the same silicon substrate. / Graduation date: 2003

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.

Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

This dissertation presents the research on several different projects. The first project is a via-less CPW RF probe pad to microstrip transition; The second, the third, and the fourth one are reconfigurable microwave circuits using RF MEMS switches: an X-band reconfigurable bandstop filter for wireless RF frontends, an X-band reconfigurable impedance tuner for a class-E high efficiency power amplifier using RF MEMS switches, and a reconfigurable self-similar antenna using RF MEMS switches. The first project was developed in order to facilitate the on-wafer measurement for the second and the third project, since both of them are microstrip transmission line based microwave circuits. A thorough study of the via-less CPW RF probe pad to microstrip transition on silicon substrates was performed and general design rules are derived to provide design guidelines. This research work is then expanded to W-band via-less transition up to 110 GHz. The second project is to develop a low power reconfigurable monolithic bandstop filter operating at 8, 10, 13, and 15 GHz with cantilever beam capacitive MEMS switches. The filter contains microstrip lines and radial stubs that provide different reactances at different frequencies. By electrically actuating different MEMS switches, the different reactances from different radial stubs connecting to these switches will be selected, thus, the filter will resonate at different frequencies. The third project is to develop a monolithic reconfigurable impedance tuner at 10 GHz with the cantilever DC contact MEMS switch. The impedance tuner is a two port network based on a 3bit-3bit digital design, and uses 6 radial shunt stubs that can be selected via integrated DC contact MEMS switches. By selecting different states of the switches, there will be a total of 2^6 = 64 states, which means 64 different impedances will be generated at the output port of the tuner. This will provide a sufficient tuning range for the output port of the power amplifier to maximize the power efficiency. The last project is to integrate the DC contact RF MEMS switches with self-similar planar antennas, to provide a reconfigurable antenna system that radiates with similar patterns over a wide range of frequencies.

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.

A comprehensive study of the High-pass/Low-pass topology has been performed, increasing the understanding of error sources arising from bit layout issues and fabrication tolerances. This included a detailed analysis of error sources in monolithic microwave phase shifters due to device size limitations, inductor parasitics, loading effects, and non-ideal switches. Each component utilized in the implementation of a monolithic high-low pass phase shifter was analyzed, with its influence on phase behavior shown in detail. An emphasis was placed on the net impact on absolute phase variation, which is critical to the system performance of a phased array radar system. The design of the individual phase shifter filter sections, and the influence of bit ordering on overall performance was also addressed. A variety of X-band four- and five-bit phase shifters were fabricated in a 200 GHz SiGe HBT BiCMOS technology platform, and further served to validate the analysis and design methodology. The SiGe phase shifter can be successfully incorporated into a single-chip T/R module forming a system-on-a-chip (SoC). Reduction in the physical size of transmission lines was shown to be a possibility with spinel magnetic nanoparticle films. The signal transmission properties of phase lines treated with nanoparticle thin films were examined, showing the potential for significant size reduction in both delay line and High-pass/Low-pass phase topologies. Wide-band, low-loss, and near-hermetic packaging techniques for RF MEMS devices were presented. A thermal compression bonding technique compatible with standard IC fabrication techniques was shown, that uses a low temperature thermal compression bonding method that avoids plastic deformations of the MEMS membrane. Ultimately, a system-on-a-package (SoP) approach was demonstrated that utilized packaged RF MEMS switches to maintain the performance of the SiGe phase shifter with much lower loss. The extremely competitive performance of the MEMS-based High-pass/Low-pass phase shifter, despite the lack of the extensive toolkits and commercial fabrication facilities employed with the active-based SiGe phase shifters, confirms both the effectiveness of the detailed phase error analysis presented in this work and the robust nature of the High-pass/Low-pass topology.

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.

In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. / A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. / The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities. / Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.

In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.