During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.

The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex. Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply. / The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex.Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply.

The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex.Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply.

<p>Impulsni generator predstavlja jedan od najvažnijih delova bežičnog<br />primopredajnika. Pored toga što treba da generiše signal čiji<br />spektar zadovoljava odgovarajuću spektralnu masku, generator treba da<br />bude što jednostavniji, zauzima malu površinu i ima malu potrošnju.<br />Naučni doprinos ove doktorske disertacije predstavlja sedam novih<br />konfiguracija ultra-širokopojasnih impulsnih generatora<br />projektovanih u CMOS tehnologiji, od kojih su tri fabrikovane u<br />0,18 &mu;m UMC CMOS procesu. Prvi dizajn je zasnovan na principu<br />kombinovanja kratkotrajnih impulsa, sledeća tri sadrže ring<br />oscilator, naredna dva impulsna generatora koriste princip<br />filtriranja, dok poslednje novo rešenje obezbeđuje BPSK kodovanje<br />korišćenjem dva ring oscilatora.</p> / <p>Pulse generator is one of the most important parts of a wireless transceiver.<br />Besides generating a signal which spectrum has to satisfy corresponding<br />spectral mask, the pulse generator should have topology as simple as<br />possible, consume low power and occupy low die-area. Scientific contribution<br />of this dissertation are seven novel IR-UWB pulse generator architectures<br />designed in CMOS technology of which three are fabricated in 0.18 &mu;m UMC<br />CMOS process. The first design is based on combining very short pulses, the<br />next three contain a ring oscillator topology followed by two pulse generators<br />that use the filtering approach, while the last new solution enables BPSK<br />modulation by employing two ring oscillator topologies.</p>

Le test en production des circuits intégrés analogiques RF (Radio Fréquences) est coûteux aussi bien en ressources (équipement spécifique) qu'en temps. Afin de réduire le coût du test, des techniques de DfT (Design for Test) et d'auto test (BIST, Built-in-Self-Test) sont envisagées bien qu'actuellement inutilisées par l'industrie du semi-conducteur. Dans cette thèse, nous concevons et évaluons une technique d'auto test pour un amplificateur faible bruit (LNA, Low Noise Amplifier) RF. Cette technique utilise des capteurs intégrés pour la mesure du courant de consommation et de la tension en sortie du circuit à tester. Ces capteurs fournissent en sortie un signal basse fréquence. La qualité de la technique de BIST est évaluée en fonction des métriques de test qui tiennent compte des déviations du process et de la présence de fautes catastrophiques et paramétriques. Pour obtenir une estimation des métriques de test avec une précision de parts-par-million, un premier échantillonnage du circuit à tester est obtenu par simulation électrique Monte Carlo. Par la suite, un modèle statistique de la densité de probabilité conjointe des performances et des mesures de test du circuit est obtenu. Finalement, l'échantillonnage de ce modèle statistique nous permet la génération d'un million de circuits. Cette population est alors utilisée pour la fixation des limites de test des capteurs et le calcul des métriques. La technique d'auto test a été validée sur un LNA en technologie BiCMOS 0.25m, utilisant différents modèles statistiques. Une validation au niveau layout a été faite afin d'obtenir des résultats aussi proches que possible lors d'un test en production d'une population de circuits.

Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

<p>Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnog<br />primopredajnika neposredno nakon antene. NJegova uloga je da ulazni<br />signal određene frekvencije i male snage izdvoji i pojača iznad nivoa<br />šuma prijemnika. U okviru doktorske disertacije prikazane su i<br />opisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOS<br />tehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Na<br />osnovu dobijenih rezultata, u 0,18 &mu;m UMC CMOS tehnologiji<br />realizovan je i fabrikovan NŠP jednostavne topologije, koja<br />predstavlja zbir dva pristupa, pojačavačkog stepena kaskodne<br />strukture sa povratnom spregom i stepena sa višestrukim<br />iskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od<br />3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, a<br />zatim je i izvršena njegova karakterizacija.</p> / <p>In the transceiver chain the low noise amplifier (LNA) is placed in the frontend<br />of the receiver after the antenna. The LNA needs to isolate and amplify<br />received weak signal at a specific frequency above the noise level of the<br />receiver. In the scope of this doctoral dissertation methods for designing<br />ultra-wideband (UWB) LNA in CMOS technology are presented and<br />described. Nine new LNA configurations were proposed. Based on the<br />obtained results, simple LNA configuration, obtained by merging casode<br />feedback topology and current-reuse technique, was realized and fabricated<br />in 0.18 &mu;m UMC CMOS technology. The LNA is designed for the frequency<br />band from 3.1 to 5 GHz. In addition, the method for measurement LNA<br />parameters is described and the proposed LNA was characterized.</p>

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.