Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

This thesis presents the modeling and design of memory cells for Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM). The theory of operation of STT-MRAM cells is explored, and a model to predict the transient behaviour of STT-MRAM cells is presented. A novel three-terminal Magnetic Tunneling Junction (MTJ) and its associated cell structure is also presented. The proposed cell is shown to have guaranteed read-disturbance immunity, as during a read operation the net torque acting on the storage cell always acts to refresh the stored data in the cell. A simulation study is conducted to compare the merits of the proposed device against a conventional 1 Transistor, 1 MTJ (1T1MTJ) cell, as a well as a differential 2 Transistors, 2 MTJs (2T2MTJ) cell. Simulation results confirm that the proposed device offers disturbance-free read operation while still offering performance advantages over conventional cells.

This thesis presents the modeling and design of memory cells for Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM). The theory of operation of STT-MRAM cells is explored, and a model to predict the transient behaviour of STT-MRAM cells is presented. A novel three-terminal Magnetic Tunneling Junction (MTJ) and its associated cell structure is also presented. The proposed cell is shown to have guaranteed read-disturbance immunity, as during a read operation the net torque acting on the storage cell always acts to refresh the stored data in the cell. A simulation study is conducted to compare the merits of the proposed device against a conventional 1 Transistor, 1 MTJ (1T1MTJ) cell, as a well as a differential 2 Transistors, 2 MTJs (2T2MTJ) cell. Simulation results confirm that the proposed device offers disturbance-free read operation while still offering performance advantages over conventional cells.

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 92-98).

Thesis (M.S.)--University of Missouri-Columbia, 2008. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.

Thesis (M.S.)--Florida State University, 2005. / Advisor: Dr. Kartik Gopalan, Florida State University, College of Arts and Sciences, Dept. of Computer Science. Title and description from dissertation home page (viewed June 8, 2005). Document formatted into pages; contains ix, 41pages. Includes bibliographical references.

Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications’ performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing unaccessed devices to be put into power-down mode, hence saving power to meet a certain power budget.

No description available.

Digital radiographic images are created by a variety of diagnostic imaging modalities. A multi-modality workstation, known as the Arizona Viewing Console (AVC), was designed and built by the University of Arizona Radiology Department to support research in radiographic image processing and image display. Two specially designed VMEbus components, the base image memory and the video display memory, were integrated into the AVC and are the subject of this thesis. The base image memory is a multi-ported, 8 megabyte memory array based on random access memory used for raw image storage. It supports a 10 megapixel per second image processor and can interface to a 320 megabit per second network. The video display memory utilizes video memories and is capable of displaying two independent high resolution images, each 1024 pixels by 1536 lines, on separate video monitors. In part, these two memory designs have allowed the AVC to excel as a radiographic image workstation.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaf 73. / by Oliver Chukwudi Ibe. / M.S.