Thesis (M.C.S.) - Carleton University, 2007. / Includes bibliographical references (p. 77-84). Also available in electronic format on the Internet.

Cette thèse vise principalement à faire face à la fiabilité de stockage de STT-MRAM au niveau dispositif, au niveau circuit et au niveau système. Les majeures contributions de cette thèse peuvent être résumées comme il suit: a) La modélisation de la jonction tunnel magnétique par courant polarisé en spin (STT-MTJ), pour développer un compact modèle SPICE de STT-MTJ. b) Le design de fiabilité de STT-MRAM au niveau dispositif, pour étudier les structures de base de cellule de mémoire et de cellules de référence. Dans cette partie, nous avons proposé une cellule de mémoire configurable (CMC), une cellule dynamique de référence (RDC) et un loquet magnétique de rayonnement durci (RHM-Latch). c) Le design de fiabilité de STT-MRAM au niveau circuit, pour étudier les modules de circuits périphériques. Dans cette partie, nous avons proposé un circuit de lecture séparé et précharge (SPCRC), un circuit de lecture offset-Tolérant sans perturbation (OTDFRC) et un circuit de correction d'erreur intégré. d) Le design de fiabilité de STT-MRAM au niveau système, vise principalement à étudier l'architecture de la puce. Dans cette partie, nous avons proposé une architecture reconfigurable (nommé Re-STT-MRAM) et une architecture de correction d'erreur hybride (nommé cRR-SECC). / This thesis aims mainly to deal with the storage reliability of STT-MRAM from device-Level, circuit-Level and system-Level perspectives. The major contributions of this thesis can be summarized as follows: a) Spin transfer torque magnetic tunnel junction (STT-MTJ) modeling, to develop a compact SPICE model of STT-MTJ.b) Device-Level reliability design of STT-MRAM, to study the basic memory cell and reference cell structures. We proposed a configurable memory cell (CMC), a dynamic reference cell (DRC) and a radiation hardened magnetic latch (RHM-Latch) in this part.c) Circuit-Level reliability design of STT-MRAM, to study the peripheral circuit modules. We proposed a separated pre-Charge read circuit (SPCRC), an offset-Tolerant disturbance-Free read circuit (OTDFRC) and a built-In error correction circuit in this part.d) System-Level reliability design of STT-MRAM, aims mainly to study the chip architecture. We proposed a reconfigurable architecture and a hybrid error correction architecture in this part.

With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.

The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This form of computing consists of a Look-Up Table (LUT) which is basically memory array mapped with a function; the computations thereafter consist of essentially read operations. An MBC framework requires very fast and low power read operations. Moreover, the cells need to be read stable as major part of the computation is done by reading the LUTs mapped in the SRAM array. Design and measurement of a prototype MBC test-chip with SRAM system optimized for read-heavy applications is presented in this thesis. For this purpose, a prototype MBC system was designed and taped out. Essential study of the write-ability of the core LUT is also presented. The core memory array for function table mapping was characterized for leakage, write-ability and power saving associated with pulsed read mode.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

Les capteurs monolithiques actifs à pixels (Monolithic Active Pixel Sensors, MAPS) sont de bons candidats pour être utilisés dans des expériences en Physique des Hautes Énergies (PHE) pour la détection des particules chargées. Dans les applications en PHE, des puces MAPS sont placées dans le voisinage immédiat du point d’interaction et sont directement exposées au rayonnement intense de leur environnement. Dans cette thèse, nous avons étudié et amélioré la résistance aux radiations des MAPS. Les effets principaux de l’irradiation et le progrès de la recherche sur les MAPS sont étudiés tout d'abord. Nous avons constaté que les cœurs des SRAM IP incorporées dans la puce MAPS limitent sensiblement la tolérance aux radiations de la puce MAPS entière. Aussi, pour améliorer la radiorésistance des MAPS, trois mémoires radiorésistantes sont conçues et évaluées pour les expériences en PHE. Pour remplacer les cœurs des IP SRAM, une SRAM radiorésistante est développée sur une petite surface. Pour les procédés de plus petit taille de grille des transistors, dans lequel les effets SEU (Single Event Upset) deviennent significatifs, une SRAM radiorésistante avec une tolérance SEU accrue est réalisée à l’aide d’un algorithme de détection et de correction d'erreurs (Error Detection And Correction, EDAC) et un stockage entrelacé des bits. Afin d'obtenir une tolérance aux rayonnements et une densité de micro-circuits plus élevées, une mémoire à double accès avec une cellule à 2 transistors originale est développée et évaluée pour des puces MAPS futures. Enfin, la radiorésistance des puces MAPS avec des nouveaux procédés disponibles est étudiée, et les travaux futurs sont proposés. / Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

In this study, the oxygen-deficient TiO2, SrTiO3 systems and transition metal ion (Cr or V) doped TiO2, SrTiO3 and SrZrO3 systems have been investigated. We prepared samples as polycrystals, single crystals and thin films for various desires. Their structural, physical and electronic properties were measured by bulk-sensitive techniques (X-Ray Diffraction, SQUID and Electro Paramagnetic Resonance) or surface-sensitive techniques (Photoemission spectroscopy and X-ray absorption spectroscopy). The measurement of SQUID and EPR showed not only their magnetic properties but also the valence state of Cr dopant. We verified the valence state of Cr ions in oxides and found the key parameters of sample synthesis which control the valence state of Cr ions. Segregated phases such as SrCrO4 were formed when the samples were synthesized under O2 rich environment. The surface properties of Cr doped SrZrO3 films are also discussed. We found the synthesis conditions which influence on not only the behavior of Cr ions but also the resistive-switching behaviors. Various resistive-switching behaviors seem to depend on the surface chemistry of films. We found that the accumulation of Cr3+ on film surface provides a clean interface without any non-stoichiometric oxides and that this sharp interface termination results in a good performance of resistive-switching.

High aspect ratio silicon etching used for DRAM manufacturing still remains as one of the biggest challenges in semiconductor fabrication, requiring well understood and characterized process fundamentals. In this study, physical and chemical interactions during etching silicon in capacitively coupled plasma discharges were investigated in detail for different HBr/NF3 mixed chemistries for single frequency as well as dual frequency operation and medium discharge pressures inside an industrial MERIE CCP reactor typically used for DRAM fabrication. Utilization of the dual frequency concept for separate control of ion energy and ion flux, as well as the impact on discharge properties and finally on etching at relevant substrate surfaces were studied systematically. The complex nature of multi frequency rf sheaths was both analyzed experimentally by applying mass resolved ion energy analysis, and from simulation of ion energy distributions by using a Hybrid Plasma Sheath Model. Discharge composition and etch processes were investigated by employing standard mass spectrometry, Appearance Potential Mass Spectrometry, Quantum Cascade Laser Absorption Spectroscopy, rf probe measurements, gravimetry and ellipsometry. An etch model is developed to explain limitations of silicon etching in HBr/NF3 discharges to achieve highly aniostropic etching. / Siliziumätzen mit hohen Aspektverhältnissen zur Herstellung von DRAM-Speicherstrukturen stellt nach wie vor eine der größten Herausforderungen in der Halbleiterherstellung dar und erfordert ein grundlegendes Prozessverständnis. Diese Studie beinhaltet eine umfassende und detaillierte Untersuchung physikalischer und chemischer Wechselwirkungen von Siliziumätzprozessen in kapazitiv gekoppelten HBr/NF3-Gasentladungen in einem kommerziellen, typischerweise für die DRAM-Fertigung eingesetzten MERIE CCP Reaktor mit Ein- und Zweifrequenzanregung bei mittleren Entladungsdrücken. Die Anwendung eines Zweifrequenzkonzeptes zur separaten Kontrolle von Ionenenergie und Ionenstromdichte, als auch deren Einfluss auf die Entladungseigenschaften und letztendlich auf das Ätzverhalten auf relevanten Substratoberflächen wurden systematisch untersucht. Die komplexe Natur von mehrfrequenzangeregten HF-Randschichten wurde sowohl experimentell über eine Anwendung von massenaufgelöster Ionenenergieanalyse als auch rechnerisch über Simulationen von Ionenenergieverteilungsfunktionen mit Hilfe eines hybriden Plasmarandschichtmodells analysiert. Gaszusammensetzungen verschiedener Entladungen und Ätzprozesse wurden mit Hilfe von Standard-Massenspektrometrie, Schwellwert-Massenspektrometrie, Quantenkaskaden-Laserabsorptionsspektroskopie, HF-Sondenmessungen, Gravimetrie und Ellipsometrie charakterisiert. Eine neuartige Modellvorstellung zum Siliziumätzen in HBr/NF3-Entladungsgemischen liefert eine plausible Erklärung für die Limitierung der Ätzrate zum Erreichen eines hoch anisotropen Ätzverhaltens.

Ferroelectricity is a material property were a remanent polarization exists under zero electrical field that can be reversed by applying an electrical field [1]. As consequence, two nonvolatile states exist that can be switched by an electrical field. This feature makes ferroelectrics ideally suited for nonvolatile memories with low write energy. Therefore, already in the 1950s first attempts have been made to realize ferroelectric nonvolatile memories based on ferroelectric barium titanate (BTO) crystals having evaporated electrodes on both sides [2]. The success of this approach was hindered by disturb issues that could be solved in the early 1990s by adding a transistor device as a selector [3]. Such a memory is referred to as a ferroelectric random access memory (FeRAM). Since reading of the ferroelectric polarization from a capacitor requires switching of the ferroelectric [1], the information will be destroyed and a write back is necessary. This can be avoided if the ferroelectric is placed inside of the gate stack of a MOS transistor resulting in a ferroelectric field effect transistor (FeFET) [1]. Conventional ferroelectric materials like BTO or lead- zirconium titanate (PZT) cannot be placed directly on silicon since unwanted interface reactions will occur. The necessary interface layer together with the space charge region of the transistor device leads to a rather low capacitance in series with the ferroelectric dielectric and consequently results in a strong depolarization field that has destroyed the nonvolatility of the FeFET device for many years and hinters scaling as well [4]. Today FeRAM devices are established on the market [3,5], but are limited to niche application since scaling is hindered by many integration problems associated to materials like PZT.