Real-time Embedded Systems (RTESs) have an increasing role in controlling society infrastructures that we use on a day-to-day basis. RTES behaviour is not based solely on the interactions it might have with its surrounding environment, but also on the timing requirements it induces. As a result, ensuring that an RTES behaves correctly is non-trivial, especially after adding time as a new dimension to the complexity of the testing process. This research addresses the problem of testing RTESs from Timed Automata (TA) specification by the following. First, a new Priority-based Approach (PA) for testing RTES modelled formally as UPPAAL timed automata (TA variant) is introduced. Test cases generated according to a proposed timed adequacy criterion (clock region coverage) are divided into three sets of priorities, namely boundary, out-boundary and in-boundary. The selection of which set is most appropriate for a System Under Test (SUT) can be decided by the tester according to the system type, time specified for the testing process and its budget. Second, PA is validated in comparison with four well-known timed testing approaches based on TA using Specification Mutation Analysis (SMA). To enable the validation, a set of timed and functional mutation operators based on TA is introduced. Three case studies are used to run SMA. The effectiveness of timed testing approaches are determined and contrasted according to the mutation score which shows that our PA achieves high mutation adequacy score compared with others. Third, to enhance the applicability of PA, a new testing tool (GeTeX) that deploys PA is introduced. In its current version, GeTeX supports Control Area Network (CAN) applications. GeTeX is validated by developing a prototype for that purpose. Using GeTeX, PA is also empirically validated in comparison with some TA testing approaches using a complete industrial-strength test bed. The assessment is based on fault coverage, structural coverage, the length of generated test cases and a proposed assessment factor. The assessment is based on fault coverage, structural coverage, the length of generated test cases and a proposed assessment factor. The assessment results confirmed the superiority of PA over the other test approaches. The overall assessment factor showed that structural and fault coverage scores of PA with respect to the length of its tests were better than the others proving the applicability of PA. Finally, an Analytical Hierarchy Process (AHP) decision-making framework for our PA is developed. The framework can provide testers with a systematic approach by which they can prioritise the available PA test sets that best fulfils their testing requirements. The AHP framework developed is based on the data collected heuristically from the test bed and data collected by interviewing testing experts. The framework is then validated using two testing scenarios. The decision outcomes of the AHP framework were significantly correlated to those of testing experts which demonstrated the soundness and validity of the framework.

<p>People make mistakes. Software engineers are no exception to this fact. When software engineers make mistakes, these manifest in the form of buggy software - a major problem in today's industry. The existence of bugs is commonly detected using testing, the process of executing the software and checking if its behaviour complies with the specification. As limitations in time make testing of the entire software behaviour impracticable, testers need to make informed decisions on how to test the software to detect as many bugs as possible.</p><p>In the realm of real-time systems (RTSs), software testing is made more difficult by non-deterministic factors such as interaction with the surrounding environment, (pseudo)parallelism, and timing requirements. Furthermore, RTS testing suffers from behaviour-altering perturbation from the instrumentation inserted in the system to keep track of test progress (i.e., probe effects).</p><p>In our work, we analyse the main test criteria used for traditional software testing in order to see which of these scale to, and assist in, system-level testing of multi-tasking RTSs. We focus on one of these criteria, the all definition-use paths coverage criterion, as it highlights a central aspect of non-deterministic task interaction, and investigate what is specifically required for applying this criterion to testing of multi-tasking RTSs. Further, we examine the possibility of using execution replay for probe effect-free test monitoring. We evaluate this approach in real industrial settings by means of case studies.</p><p>The contributions of this thesis are twofold: First, the use of structural test criteria in RTS system-level testing is facilitated by two different analysis methods. Second, the probe effect is handled by recording non-deterministic events during run-time, and by using this recording to create a monitorable deterministic replica of the first execution. By these contributions, this thesis shows how the non-determinism of multi-tasking RTSs can be handled during system-level testing.</p>

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Methods for performing response time analysis of real-timesystems are important, not only for their use in traditionalschedulability testing, but also for deriving bounds on outputtiming variations in control applications. Automatic controlsystems are inherently sensitive to variations in periodicityand end-to-end delays. Therefore, real-time performance needsto be considered during control design. For this purpose, anyreal-time analysis of a potential control implementation shouldproduce results that can easily be used to examine how theimplementation affects control performance. To find the maximumresponse time variation for a task, bounds on both minimum andmaximum response times are needed. A tight bound on thismaximum variation is useful in the analysis of controlperformance and can also be used to improve the results of someiterative response time analysis methods. In this thesis, threemethods for response time analysis are developed. While earlier research has focused on bounding maximumresponse times, one of the analysis methods in this thesisallows a computation of the minimum response times ofindependent fixed priority scheduled tasks. The analysis findsthe largest lower bound of response times for such tasks, whichleads to a tighter bound on the response time variations. Asecond analysis method allows exact computation of maximumresponse times for tasks whose arrival times are related byoffsets. The method is a complement to schedule simulationbased analysis, which it outperforms for systems with tasksthat may experience release jitter. A common design principle for distributed real-time systemsis to let the completion of one task trigger the start of oneor more successors. A third method supporting the analysis oftasks in such systems is described. The method extends andimproves earlier methods as it allows a generalized systemmodel and also results in tighter bounds than the originalmethods. This method has been implemented as part of a toolsetthat enables an integrated approach to the design and analysisof control systems and their implementation as distributedreal-time systems. As part of the thesis, models for describingdistributed control systems have been developed. The toolset,which is based on these models, uses the derived response timebounds in a control system performance analysis based onsimulation. The use of the toolset is exemplified in a smallcase study. <b>Keywords:</b>real-time systems, scheduling, response time,fixed priority, control, jitter, offset, schedulabilityanalysis

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Radiation-hardened processors are designed to be resilient against soft errorsbut such processors are slower than Commercial Off-The-Shelf (COTS)processors as well significantly costlier. In order to mitigate the high costs,software techniques such as task re-executions must be deployed together withadequately hardened processors to provide reliability. This leads to a huge designspace comprising of the hardening level of the processors and the numberof re-executions of each task in the system. Each configuration in this designspace represents a tradeoff between processor load, reliability and costs. The reliability comes at the price of higher costs due to higher levels of hardeningand performance degradation due to hardening or due to re-executions.Thus, the tradeoffs between performance, reliability and costs must be carefullystudied. Pertinent questions that arise in such a design scenario are — (i)how many times a task must be re-executed and (ii) what should be hardeninglevel? — such that the system reliability is satisfied. In order to evaluate such tradeoffs efficiently, in this thesis, we proposenovel framework that harnesses the computational power of Graphics ProcessingUnits (GPUs). Our framework is based on a system failure probabilityanalysis that connects the probability of failure of tasks to the overall systemreliability. Based on characteristics of this probabilistic analysis as well asreal-time deadlines, we derive bounds on the design space to prune infeasiblesolutions. Finally, we illustrate the benefits of our proposed framework withseveral experiments

This thesis presents a tool for obtaining worst-case execution time (WCET) guarantees for ARM processors. This tool is an interface between ARM¡¦s GCC compiler and the SWEET WCET analyzer. SWEET is an open-source static analyzer that derives a guaranteed upper bound on the WCET of a program. The WCET of a program is an important metric in real-time systems. The task scheduler must decide how much time to allot for each process; if the allotted time exceeds the WCET, the process can be guaranteed to always finish in time. Although the WCET value is therefore useful, it is difficult to find. But, for the purpose of guaranteeing that a process finishes on time, an upper bound on the WCET suffices. Static program analysis has been proposed as a method to derive such an upper-bound on the WCET, by means of conservatively approximating the runtime of the individual parts of a complete program. SWEET is one such static analyzer. Our tool works inside of ARM-GCC, extracting all of the information that SWEET needs about the program¡¦s behavior. Our tool then packages the information into the SWEET¡¦s ALF format. The tool has been tested and works correctly for every input source that we have tested (including all 34 benchmarks from the WCET BENCHMARK SUITE[1]). This work was funded by Taiwan¡¦s National Science Council, grant NSC 97-2218-E-110-003

Scratchpad memory (SPM) is popular for real-time embedded systems. Whereas caches use a memory management unit (MMU) to control which data accesses go to the fast, on-chip SRAM, SPM directly maps certain addresses to the SRAM. One advantage of SPM is that it avoids the cache¡¦s costly MMU. Another advantage is that the SPM is 100% statically predictable, whereas the variables stored in the cache depend upon the dynamic execution history. This predictability is beneficial for real-time systems which must schedule tasks to finish by fixed deadlines. To set these deadlines, system designers must determine the worst-case execution times (WCETs) of the applications. The predictability of SPM makes these WCETs easier to measure. This thesis presents a new method for allocating stack and global data to the SPM. It is the first method to make use of the special properties of non-escaping variables so as to increase the effective size of the SPM. Our insight is that many local variables of caller functions can be temporarily swapped out of the SPM while the callee function executes. Ours is also the first method to support profiled WCET measurements in the allocation strategy. Most previous SPM methods optimize only for the average-case execution time (ACET), despite the fact that SPMs are often used in real-time environments where the WCET is also important. This new memory allocation strategy is also the first to be WCET/ACET tunable, a feature that is particular useful for soft real-time systems. Only one previous work considers a WCET-targeted SPM allocator. That work, however, only applies to static WCET analysis tools. Such tools are difficult to program and are not widely used. Also, they only have application to the most safety-critical of real-time systems. In contrast, our approach is the first to employ measurement-based WCET analysis (such as is most commonly used in industry) for SPM allocation.

<p>An event monitor is a part of a real-time system that can be used to</p><p>check if the system follows the specifications posed on its behavior. This dissertation covers an approach to event monitoring where such specifications (represented by time constraints) are represented by graphs.</p><p>Not much work has previously been done on designing and implementing constraint graph-based event monitors. In this work, we focus on presenting an extensible design for such an event monitor. We also evaluate different data structure types (linked lists, dynamic arrays, and static arrays) that can be used for representing the constraint graphs internally. This is done by creating an event monitor implementation, and conducting a number of benchmarks where the time used by the monitor is measured.</p><p>The result is presented in the form of a design specification and a summary of the benchmark results. Dynamic arrays are found to be the generally most efficient, but advantages and disadvantages of all the data structure types are discussed.</p>

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