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Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support.

"As research in the field of mobile robotics continues to advance, legged robots in different forms and shapes find a variety of applications on rough terrain where wheeled robots fail to operate in practice. For this reason, a modular legged robot platform is being developed at WPI. This research focuses on developing a mathematical model and then building a simulation to verify the model for a single leg for this platform. The robot platform is modular in the sense that leg modules can be removed and added to predetermined ports on the robot chassis. The modularity of a legged robot is a significant advancement in mobile robotics technology as it enables a single robot to take on different body configurations depending on circumstances and environment to achieve its goals. It also poses a challenge in terms of overall design as it requires autonomous operation of the leg. The goal for this research is to in part fulfill the need for a mathematical model for an autonomous leg. This research investigates the development of a kinematic and dynamic model for the leg, a step trajectory for walking, a simulation of the system to verify the dynamic model, and various functions and scripts to identify shortcomings within the model. This research uses Mathworks Matlab and Wolfram Mathematica to develop the mathematical model, and Matlab Simulink SimMechanics and Matlab functions to build a simulation. Both the mathematical model and simulation follow the classic design of other legged robots, utilizing Lagrangian dynamics, the Jacobian, and simulation tools. The result is a project that is unique in that it drives a robot leg almost independently with very limited communication to a central controller."

It has been proofed that Reconfigurable Computing System possesses the potential to promote system efficiency. Fine-Grain Reconfigurable Computing System, which integrates the co-design of software and hardware, is the prevailing current in system designing with low clock rate and high efficiency. The thesis focuses on computing-oriented Fine-Grain Reconfigurable Computing System of software-hardware interwork, and setting up invoking working model for software program and hardware module as well. The designing of software and hardware can be integrated into one program, which deals with the hardware as a function. By quick computing of hardware, it can promote system efficiency. This interwork mechanism can be combined into traditional instruction execute pipeline. It composes manageable Fine-Grain for Reconfigurable Computing System as a new processor architecture, which brings up new command to support execution of software-hardware interwork mechanism. The model architecture is verified by algorithms of multimedia application, such as Motion Estimation and DCT. In addition, it presents the optimizing model by analysis and comparison of software and hardware efficiency.

At present the scale of multimedia and communication systems has become more and more complicated due to the fast development of them. In order to improve the capability of real-time processing and shorten system development time, the ability to reconfigure system architecture becomes an important and flexible design consideration. In this thesis, we propose a reconfigurable processing unit, FMRPU, which is a fine-grain multi-context reconfigurable processing unit targeting at high-throughput and data-parallel applications. It contains 64 reconfigurable logic arrays, 16 switch boxes, and connects with each other via three hierarchical-level connectivities. To avoid the excessive routing path to be the bottleneck of mapped circuits, we design the data stream switch to rearrange data streams. According to the simulation results, the longest routing path of FMRPU only takes 6.5 ns at 0.35 processes, which is able to construct the required logic circuit efficiently. Compare with same kind devices in dealing with Motion Estimation operations, the performance is raise to 17% and is excellent to other same kind architectures in executing other DSP algorithms.

This thesis focuses on the design of radio-frequency (RF) mixers, including a broadband downconverter mixer, an upconverter mixer and a downconverter mixer with high linearity. The basic mixer topology used in this thesis was the Gilbert cell mixer, which is the most popular mixer topology in modern communication systems. In order to accommodate different applications, the broadband mixer and the upconverter mixer were designed to be reconfigurable. First, a broadband downconverter mixer with variable conversion gain was designed using 0.13-$\mu m$ CMOS technology. The mixer worked from 2 to 10 GHz. By changing the effective transistor size of the transconductor and the load, the mixer was able to work in three different modes with different conversion gain and power consumption. Second, an upconverter mixer with sideband selection was demonstrated in CMOS 0.13-$\mu$m technology. The transmitted sideband could be chosen to be the upper sideband or the lower sideband. The mixer worked at 5 GHz with a 100 MHz IF. The measured voltage conversion gains were 11.2 dB at 4.9 GHz and 12.4 dB at 5.1 GHz. The best sideband rejection was around 30 dB. Third, a modified derivative superposition (DS) technique was used to linearize a Gilbert cell mixer. Simulation results predicted an IIP3 improvement of 12.5 dB at 1 GHz. After linearization, the noise figure of the mixer increased by only 0.7 dB and the conversion gain decreased by 0.3 dB. The power consumption of the mixer increased by 0.96 mW. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-18 14:40:35.062

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FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables dynamic modular design, which sacrifices some design speed and area optimization for faster implementation of layout changes, including addition of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools. / Master of Science

Reconfigurable antennas represent a recent innovation in antenna design that changes from classical fixed-form, fixed-function antennas to modifiable structures that can be adapted to fit the requirements of a time varying system. Advances in microwave semiconductor processing technologies have enabled the use of compact, ultra-high quality RF and microwave switches in novel aspects of antenna design. This dissertation introduces the concept of reconfigurable antenna bandwidth control and how advances in switch technology have made these designs realizable. Specifically, it details the development of three new antennas capable of reconfigurable bandwidth control. The newly developed antennas include the reconfigurable ring patch, the reconfigurable planar inverted-F and the reconfigurable parasitic folded dipole. The relevant background work to these designs is described and then design details along with computer simulations and measured experimental results are given. / Ph. D.

FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts. / Master of Science