The Software Communications Architecture (SCA) is a standard for software defined radios (SDR) designed in part to promote code reuse for long-term development. With the emergence of adaptive/cognitive radios, new SDRs that are capable of reconfiguration during runtime must be developed. One advantage of SDR development over conventional radio development can be ease of design if the proper rapid development tools are made available. This thesis explores tools designed to help realize the construction of reconfigurable systems while promoting code-reuse within the bounds of the SCA. Developing these tools requires an understanding of the SCA as well as the Open Source SCA Implementation Embedded (OSSIE) for which they are developed. The use of CORBA to link together modularized components is also discussed. Finally, several simulations are conducted in order to approximate the amount of overhead resulting from the use of the reconfiguration tool developed (the "Connect Tool"). / Master of Science

The next generation of wireless communications will demand the use of software radio technology as the basic architecture to support multi-standard, multi-mode and future-proof radio designs. Software-defined radios are configurable devices in which the physical layer can be reprogrammed to support various standards. Field programmable architectures provide a suitable platform to achieve such run-time reconfigurations of the physical layer of the radio. This thesis explores the use of FPGAs in the design of reconfigurable radios. The results presented here demonstrate how FPGAs can be used to provide the flexibility, performance, efficiency and better resource utilization while meeting the speed and area constraints set by a particular design. The partial reconfiguration feature available in the state-of-the art FPGAs has been exploited to implement the baseband physical layer of reconfigurable radio which can be altered to support various modulations schemes for different wireless standards. The design flow for partial reconfiguration along with the implementation results on two different FPGA platforms is presented. The experiments presented in this thesis make use of System Generator for DSP, a productivity tool from Xilinx, to design and to simulate system-level models in a MATLAB/Simulink environment, and to obtain timing and resource utilization results before implementing the design on actual hardware. / Master of Science

No description available.

Les équipements de communications numériques intègrent de plus en plus de standards. La commutation d’un standard à l’autre doit pouvoir se faire au prix d’un surcoût matériel modéré, ce qui impose l’utilisation de ressources communes dans des instanciations différentes. La plateforme matérielle nécessaire à l’exécution d’une couche physique multistandard est le segment du système présentant le plus de contraintes par rapport à la reconfiguration : réactivité, consommation et occupation de ressources matérielles. Nos travaux se focalisent sur la paramétrisation qui vise une implémentation multistandards efficace. L’objectif de cette technique est d’identifier des traitements communs entre les standards, voire entre blocs de traitement au sein d’un même standard, afin de définir des blocs génériques pouvant être réutilisés facilement. Nous définissons le management d’opérateurs mutualisés (opérateurs communs) et nous étudions leur implémentation en se basant essentiellement sur des évaluations de complexité pour quelques standards utilisant la modulation OFDM. Nous proposons en particulier l’architecture d’un opérateur commun permettant la gestion efficace des ressources matérielles entre les algorithmes FFT et décodage de Viterbi. L’architecture, que nous avons proposé et implémenté sur FPGA, permet d’adapter le nombre d’opérateurs communs alloués à chaque algorithme et donc permet l’accélération des traitements. Les résultats montrent que l’utilisation de cette architecture commune offre des gains en complexité pouvant atteindre 30% dans les configurations testées par rapport à une implémentation classique avec une réduction importante de l’occupation mémoire. / Today's telecommunication systems require more and more flexibility, and reconfiguration mechanisms are becoming major topics especially when it comes to multistandard designs. In typical hardware designs, the communication standards are implemented separately using dedicated instantiations which are difficult to upgrade for the support of new features. To overcome these issues, we exploit a parameterization approach called the Common Operator (CO) technique that can be considered to build a generic terminal capable of supporting a large range of communication standards. The main principle of the CO technique is to identify common elements based on smaller structures that could be widely reused across signal processing functions. This technique aims at designing a scalable digital signal processing platform based on medium granularity operators, larger than basic logic cells and smaller than signal processing functions. In this thesis, the CO technique is applied to two widely used algorithms in wireless communication systems: Viterbi decoding and Fast Fourier Transform (FFT). Implementing the FFT and Viterbi algorithms in a multistandard context through a common architecture poses significant architectural constraints. Thus, we focus on the design of a flexible processor to manage the COs and take advantage from structural similarities between FFT and Viterbi trellis. A flexible FFT/Viterbi processor was proposed and implemented on FPGA and compared to dedicated hardware implementations. The results show a considerable gain in flexibility. This gain is achieved with no complexity overhead since the complexity if even decreased up to 30% in the considered configurations.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.