The construction industry is known for its high accident rate which leads to numerous fatalities every year. Currently, the Occupational Safety and Health Administration (OSHA) requires injury/illness recording forms to be completed only for injuries requiring medical treatment and fatalities. The assertion of this paper is that underlying problems can be best determined through the causes of first-aid injuries that have the potential to prevent serious injuries in the future. Therefore, by classifying and recording first-aid cases on project sites, the common trend type of injury can be followed and appropriate measures can be taken to eliminate hazards. The main objective of this research is to establish a comprehensive standardized database to record first-aid injury cases, injuries requiring medical treatment and fatalities all in one. The recording format described in this research will facilitate the analysis of the data in a more effective manner which can subsequently be used to develop pre-emptive measures to eliminate common causes for construction injuries. In order, to create the Form, 900 sets of injury data were obtained from an industrial construction firm and analyzed. These data provided a good indication of the classification system adopted by industries today. The proposed Injury and Illness Database/Form (I

Neural recording systems have attracted an increasing amount of attention in recent years, and researchers have put major efforts into designing and developing devices that can record and monitor neural activity. Understanding the functionality of neurons can be used to develop neuroprosthetics for restoring damages in the nervous system. An analog front-end block is one of the main components in such systems, by which the neuron signals are amplified and processed for further analysis. In this work, our goal is to design and implement a field-programmable 16-channel analog front-end block, where its programmability is used to deal with process variation in the chip. Each channel consists of a two-stage amplifier as well as a band-pass filter with digitally tunable low corner frequency. The 16 recording channels are designed using four different architectures. The first group of recording channels employs one low-noise amplifier (LNA) as the first-stage amplifier and a fully differential amplifier for the second stage along with an NMOS transistor in the feedback loop. In the second group of architectures, we use an LNA as the first stage and a single-ended amplifier for implementing the second stage. Groups three and four have the same design as groups one and two; however the NMOS transistor in the feedback loop is replaced by two PMOS transistors. In our design, the circuits are optimized for low noise and low power consumption. Simulations result in input-referred noise of 6.9 ??Vrms over 0.1 Hz to 1 GHz. Our experiments show the recording channel has a gain of 77.5 dB. The chip is fabricated in AMS 0.35 ??m CMOS technology for a total die area of 3 mm??3 mm and consumes 2.7 mW power from a 3.3 V supply. Moreover, the chip is tested on a PCB board that can be employed for in-vivo recording.

This thesis presents a bio-signal recording system with offset cancellation and a low power comparator. The recording of bio-signal requires high-gain amplification before recording, to match the input to the range of the analog to digital converter (ADC); interference could be a problem if it causes the amplifier to reach saturation, leaving the recording inoperable (i.e., blank) until it returns to its normal state. The proposed system can monitor the amplifier output, and reset the amplifier output to a point near the center of its dynamic range before the amplifier output leaves its dynamic range. The proposed system provides discrete compensation voltages to cancel the offset voltage, and thereby avoids the shortcomings of conventional filters. Furthermore, a low power and low offset voltage comparator for low current operation is proposed. It is suitable for the clock controller in a sampled bio-signal acquisition system. The measured current consumption of the comparator is less than 130 nA, and the offset voltage is 2 mV. The proposed recording system and comparator have been implemented in the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35£gm 2P4M CMOS process technology to verify the simulation results as well as the correctness of the proposed architecture.

Globally, anurans have experienced significant declines and reliable monitoring protocols are required to track population trends. This thesis compares the effectiveness of manual call surveys (MCS) and automated recording systems (ARS) and describes the calling profiles of seven anuran species in southern Ontario. Using detailed audio recordings, we identify the seasonal and hourly calling patterns of seven anuran species at Warwick and Silver Creek Conservation Areas in the Credit River watershed. We employ descriptive and graphical methods to establish calling profiles. Given the low detection rate of American toads, grey treefrogs and northern leopard frogs, a survey protocol comprised of 9 weekly site visits are recommended in May and June. The optimal time of day for detecting the greatest abundance and species richness is 23h30 whereas optimal survey duration varies with hour and season given the target species. Climatic variables may induce or inhibit call activity and until the extent of these variables can be established, protocol guidelines should implement longer and more frequent site visits. The urgency of this revision is exacerbated for commercial surveys used to make contentious land management decisions.

This work presents a high-voltage, high-precision bi-directional multi-channel system capable of stimulating neural activity through bi-phasic pulses of amplitude up to ∓50 V while recording very low-voltage responses as low as tens of microvolts. Most of the systems reported from the scientific community possess at least one of the following common limitations: low stimulation voltages, low gain capabilities, or insufficient bandwidth to acquire a wide range of different neural activities. While systems can be found that present remarkable capabilities in one or more specific areas, a versatile system that performs over all these aspects is missing. Moreover, as many novel materials, like silicon carbide, are emerging as biocompatible interfaces, and more specifically as neuronal interfaces, it becomes mandatory to have a system operating across a wide range of voltages and frequencies for both physiological and electrical compatibility testing. The system designed and proven during this doctoral research effort features a ∓50 V bi-phasic pulse generator, 62 to 100 dB of software selectable amplification, and a wide 18 Hz to 12 kHz bandwidth. In addition to design and realization we report about biological testing consisting in the acquisition of neural signals from tissue cultures using an MEA where faithful signal recording was achieved with superior fidelity to a commercial system used to sample signals from the same culture. The only system parameter that was less robust than the commercial system was the noise level, which due to our higher bandwidth was somewhat expected. More importantly our custom electronics outperformed in terms of lower delay and lower cost of realization. All of these results plus suggested future works are listed for the reader's convenience.

Elektroencefalografický záznamový systém slouží k vyšetření mozkové aktivity. Na základě tohoto vyšetření lze stanovit diagnózu některých nemocí, například epilepsie. Účelem této práce bylo zpracování signálu z toho systému a vytvoření modelového signálu, který bude s reálným signálem porovnán. Uměle vytvořený signál vychází z Jansenova matematického modelu, který byl dále implementován v prostředí MATLAB a rozšířen ze základního modelu na komplexnější zahrnující nelinearity a model rozhraní elektroda – elektrolyt. Dále bylo provedeno měření signálů na EEG fantomu a následná identifikace parametrů naměřených signálu. V první fázi byly testovány jednoduché signály. Identifikace parametrů těchto signálů sloužila k validaci daného EEG fantomu. V druhé fázi bylo přistoupeno k testování EEG signálů navržených podle matematického Jansenova modelu. Analýza veškerých signálů zahrnuje mimo jiné časově frekvenční analýzu či ověření platnosti principu superpozice.

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.