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Power consumption is a critical design issue in embedded processors. As part of our low power processor design project, this thesis work aims to reduce power consumption on two typical processor components: Register File (RF), and Arithmetic and Logic Unit (ALU). Register File is one of the most power hungry components in the processor, consuming about 20% of the processor power. The ALU is the working horse in the processor, responsible for almost all basic computing operations. Although ALU does not consume as high power as the register file, we observe that it can be power intensive in terms of power dissipation per silicon area unit and may result in a thermal hot spot in the processor. Existing approaches to reduce power on the register file and ALU are effective. However, most of them either entail extensive hardware design efforts, or require a significant amount of work on post-compilation software code modification. The approaches proposed in this thesis avoid such problems. We only customize the internal structure of the processor components and keep the components’ interface to other system parts intact, so that the customization to a component is transparent to its external hardware design and no modification/alteration to other hardware components or to the software code is required. This customization strategy is well suitable to our whole low power processor design project and can be applied to any customization of an existing system for a given application. We have applied our customization approaches to a set of benchmarks in a variety of application domains. Our experimental results show that the power savings on register file are in a range from 18.8% to 45.5%, an average of 29.7% register file power can be saved. For the arithmetic and logic unit, the power savings are from 43.5% to 49.6% and the average saving is 46.9% as compared to the original designs. We also combine the customization of both the ALU and the register file. With the customizing of the ALU and the register file simultaneously, the processor power consumption can be reduced from 3.9% to 10.1%; on average, 6.44% processor power can be saved. Most importantly, the power saving achievement is at the cost of neither hardware complexity nor processor performance, and the implementation is extremely straightforward and can be easily incorporated into a processor design environment, such as ASIPMeister (a design tool, to automatically generate a VHDL model for application specificinstruction set processors) used in our research.

Asthma, a huge burden on millions of individuals worldwide, is one of the most important public health issues in many countries. As genetic and   environmental factors interact, asthma may be programmed very early in life, perhaps even in utero. The aim of this thesis was to assess the impact of gestational age, cord blood immunoglobulin E (IgE), a family history of asthma, migration, and pertussis immunization in early life on the development of asthma in child and adult populations. As a proxy for asthma disease, dispensed asthma medication was used as the main outcome variable based on data from the Swedish Prescribed Drug  Register. Data from other national registers were used to control for  confounders. Three of our studies were based on national cohorts, and one on a local birth cohort that was initiated in 1974–75. Gestational age had an inverse dose-response relationship with dispensed asthma medication in 6– to 19-year-olds. Odds ratios for dispensed asthma medication increased with degree of prematurity compared with children born in term. Furthermore, asthma medication was more likely to be dispensed among children and adolescents born early term after 37–38 weeks’ gestation than among those at the same age who were born in term. Elevated cord blood IgE and a family history of asthma in infancy were associated with a two- to threefold increased likelihood of dispensed asthma medication and self-reported allergen-induced respiratory symptoms at the age of 32–34 years, but the predictive power was poor. Age at migration had an inverse dose-response relationship with dispensed asthma medication at the age of 6–25 years in adoptees and foreign-born children with foreign-born parents. International adoptees and children born in Sweden to foreign-born parents had three- to fourfold higher rates of asthma medication compared with foreign-born children who were raised by their foreign-born birth parents. No association was found between pertussis immunization in early infancy and dispensed asthma medication in 15-year-olds. The type of vaccine or vaccine schedule did not affect the outcome. Fetal life is a vulnerable period. This thesis strengthens the evidence that every week of gestation is important for lung maturation. Cord blood IgE, however, did not predict the risk of asthma in adults. Furthermore, the study of migrating populations demonstrated that environmental changes at any age during childhood may affect the risk of asthma. Another, important public health message from this thesis is that vaccination against pertussis in early childhood can be considered safe with respect to the long-term development of asthma.

Conventional processor design utilizes a central register file and a bypass network to deliver operands to and from functional units, which cannot scale to a large number of functional units. As more functional units are integrated into a processor, the number of ports on a register file grows linearly while area, delay, and energy consumption grow even more rapidly. Physical properties of a bypass network scale in a similar manner. In this dissertation, a fully distributed register file organization is presented to overcome this limitation by relying on small register files with fewer ports and localized operand bypasses. Unlike other clustered microarchitectures, each cluster features a small single-issue functional unit coupled with a small local register file. Several clusters are used, and each of them can be different. All register files are connected through a register transfer network that supports multicast communications. Techniques to support distributed register file operations are presented for both dynamically and statically scheduled processors. These include the eager and multicast register transfer mechanisms in the dynamic approach and the global data routing with multicasting algorithm in the static approach. Although this organizaiton requires additional cycles to execute a program, it is compensated by significant savings obtained through smaller area, faster operand access time, and lower energy consumption. With faster operating frequency and more efficient hardware implementation, overall performance can be improved. Additionally, the fully distributed register file organization is applied to an ILP-SIMD processing element, which is the major building block of a massively parallel media processor array. The results show reduction in die area, which can be utilized to implement additional processing elements. Consequently, performance is improved through a higher degree of data parallelism through a larger processor array. In summary, the fully distributed register file architecture permits future processors to scale to a large number of functional units. This is especially desirable in high-throughput processors such as wide-issue processors and multithreaded processors. Moreover, localized communication is highly desirable in the transition to future deep submicron technologies since long wire is a critical issue in processes with extremely small feature sizes.

Network processors are custom high performance embedded processors deployed for a variety of tasks that must operate at high line (Gbits/sec) speeds to prevent packet loss. With the increase in complexity of application domains and larger code store on modern network processors, the network processor programming goes beyond simply exploiting parallelism in packet processing. Unlike the traditional homogeneous threading model, modern network processor programming must support heterogenous threads that execute simultaneously on a microengine. In order to support such demands, we first propose hardware management of registers across multiple threads. In their PLDI 2004 paper, Zhuang and Pande for the first time proposed a compiler based scheme to support register allocation across threads; in this work, we extend their static allocation method to support aggressive register allocation taking dynamic context into account. We also remove the load/stores due to aliased memory accesses converting them into register moves exploiting dead registers. This results in tremendous savings in latency and higher throughput mainly due to the removal of high latency accesses as well as idle cycles. The dynamic register allocator is designed to be light-weight and low latency by undertaking many tradeoffs. In the second part of this work, our goal is to design an automatic register allocation scheme that makes compiler transperant to dual bank register file design for network processors. By design network processors mandate that the operands of an instruction must be allocated to registers belonging to two different banks. The key goal in this work is to take into account dynamic contexts to balance the register pressure across the banks. Key decisions made involve, how and where to map incoming virtual register on a physical register in the bank, how to evict dead ones, and how to minimally undertake bank to bank copies and swaps. It is shown that it is viable to solve both of these problems by simple hardware designs that avail of dynamic contexts. The performance gains are substantial and due to simplicity of the designs (which are also off critical paths) such schemes may be attractive in practice.

The University of Arizona catalogs contain information regarding curricula, fees, university policies, and procedures.

The University of Arizona catalogs contain information regarding curricula, fees, university policies, and procedures.

The University of Arizona catalogs contain information regarding curricula, fees, university policies, and procedures.

The University of Arizona catalogs contain information regarding curricula, fees, university policies, and procedures.

The University of Arizona catalogs contain information regarding curricula, fees, university policies, and procedures.