The particular purpose of this study was to determine the effects of large-scale sagebrush reseeding projects on sage grouse populations and whether such effects were partly or entirely beneficial, neutral, or detrimental to the survival of such populations. During two seasons of field work, the studies initiated on a short-time basis had the following specific objectives: To compare the utilization by sage grouse of reseeded and non-reseeded lands for the seasonal activities of mating, nesting, raising a brood, fall coveying, and wintering. To compare the utilization by sage grouse of reseeded and non-reseeded lands for daily activities of feeding, watering, resting, hiding, and roosting. To determine fall and winter movements of the grouse in relation to reseeded lands. To determine the food and cover available to grouse on randomly selected sample plots To arrive at an index to food preferences through comparison of stomach analysis and food availability studies. To determine the effect of livestock grazing of reseeded lands on sage grouse. To determine the effect of plant succession on availability of food and cover within reseeded lands.

abstract: Baseline community composition data provides a snapshot in time that allows changes in composition to be monitored more effectively and can inform best practices. This study examines Arizona Upland plant community composition of the Sonoran Desert through three different lenses: floristic inventory, and fire and reseeding effects. A floristic inventory was conducted at Cave Creek Regional Park (CCRP), Maricopa County, AZ. One hundred fifty-four taxa were documented within Park boundaries, including 148 species and six infraspecific taxa in 43 families. Asteraceae, Boraginaceae, and Fabaceae accounted for 40% of documented species and annuals accounted for 56% of documented diversity. Fire effects were studied at three locations within McDowell Sonoran Preserve (MSP), Scottsdale, AZ. These fires occurred throughout the 1990s and recovered naturally. Fire and reseeding effects were studied at the site of a 2005 fire within CCRP that was reseeded immediately following the fire. Two questions underlie the study regarding fire and reseeding effects: 1) How did fire and reseeding affect the cover and diversity of the plant communities? 2) Is there a difference in distribution of cover between treatments for individual species or growth habits? To address these questions, I compared burned and adjacent unburned treatments at each site, with an additional reseeded treatment added at CCRP. MSP sites revealed overall diversity and cover was similar between treatments, but succulent cover was significantly reduced, and subshrub cover was significantly greater in the burn treatment. Seventeen species showed significant difference in distribution of cover between treatments. The CCRP reseeded site revealed 11 of 28 species used in the seed mix persist 12 years post-fire. The reseeded treatment showed greater overall diversity than burned and unburned treatments. Succulent and shrub cover were significantly reduced by fire while subshrub cover was significantly greater in the reseeded treatment. Sixteen species showed significant difference in distribution of cover between treatments. Fire appears to impact plant community composition across Arizona Upland sites. Choosing species to include in seed mixes for post-fire reseeding, based on knowledge of pre-fire species composition and individual species’ fire responses, may be a useful tool to promote post-fire plant community recovery. / Dissertation/Thesis / Masters Thesis Plant Biology and Conservation 2018

Η συνεχής μείωση των διαστάσεων των ψηφιακών κυκλωμάτων σε συνδυασμό με την ολοένα αυξανόμενη πολυπλοκότητά τους, έχει οδηγήσει στην απαίτηση για αξιοπιστία και συνεπώς στην εφαρμογή τεχνικών ελέγχου για την εξασφάλιση της ορθής λειτουργίας τους. Οι βασικοί τρόποι εφαρμογής του ελέγχου σε ένα κύκλωμα μετά την κατασκευή του και την τοποθέτησή του στη συσκευασία είναι ο εξωτερικός (off-chip – εξολοκλήρου χρήση εξωτερικού ελεγκτή ATE), ο BIST (Built-In Self Test – μηδενική χρήση ATE) και ο ενσωματωμένος (embedded – συνδυασμός χρήσης ATE με ενσωματωμένες δομές ελέγχου). Η συγκεκριμένη διπλωματική εργασία επικεντρώνεται στη χρήση του ενσωματωμένου ελέγχου και συγκεκριμένα σε μια κατηγορία αυτού που ονομάζεται εμφώλευση συνόλου δοκιμής (test set embedding) στην οποία το σύνολο δοκιμής ενσωματώνεται σε μια μεγαλύτερη ακολουθία καταστάσεων ενός κυκλώματος παραγωγής διανυσμάτων δοκιμής. Σε αυτή τη διπλωματική εργασία προτείνεται μια νέα μέθοδος για ενσωματωμένο έλεγχο που κάνει χρήση της ανατροφοδότησης (reseeding) για έλεγχο με χρήση ολισθητή γραμμικής ανάδρασης (LFSR). Η μέθοδος αυτή χρησιμοποιείται είτε σε απλές αρχιτεκτονικές ελέγχου με LFSR, είτε σε πολυφασικές αρχιτεκτονικές, πάντα για κυκλώματα με πολλαπλές αλυσίδες. Στην πολυφασική αρχιτεκτονική εκμεταλλευόμαστε τις ακολουθίες από bits που εξάγονται από διάφορες βαθμίδες ενός LFSR, το οποίο χρησιμοποιείται για την παραγωγή διανυσμάτων δοκιμής, για να κωδικοποιήσουμε το σετ ελέγχου της υπό δοκιμή λειτουργικής μονάδας. Παρουσιάζεται ένας νέος αλγόριθμος, ο οποίος περιλαμβάνει τέσσερα κριτήρια για την αποδοτική επιλογή νέων αρχικών καταστάσεων και των βαθμίδων του LFSR. Τέλος παρουσιάζεται και μια μεθοδολογία μείωσης του μήκους της παραγόμενης ακολουθίας δοκιμής. Στη συνέχεια και για να συγκρίνουμε τα αποτελέσματα που εξάγονται από την παραπάνω μέθοδο υλοποιήθηκε μια νέα τεχνική που έχει προταθεί πρόσφατα στη βιβλιογραφία. Η μέθοδος αυτή καλείται REusing Scan chains for test Pattern decompressIoN (RESPIN) και έχει κύριο χαρακτηριστικό την εμφώλευση του συνόλου δοκιμής. Σύμφωνα με τη μέθοδο αυτή η αποσυμπίεση των διανυσμάτων που ελέγχουν μια λειτουργική μονάδα γίνεται με τη χρήση αλυσίδων ελέγχου μιας δεύτερης λειτουργικής μονάδας που βρίσκεται μέσα στο chip και που τη στιγμή του ελέγχου είναι σε αδρανή κατάσταση. Έπειτα από εκτενή σύγκριση των δυο προαναφερθέντων τεχνικών καθώς και άλλων τεχνικών που αναφέρονται στη βιβλιογραφία καταλήξαμε στο συμπέρασμα ότι ο συνδυασμός του αλγόριθμου επιλογής νέων αρχικών καταστάσεων ενός LFSR με την τεχνική μείωσης των ακολουθιών ελέγχου αποτελεί ελκυστική λύση και παρέχει καλύτερα αποτελέσματα τόσο ως προς το πλήθος των δεδομένων που αποθηκεύονται στο ΑΤΕ, όσο και ως προς το μήκος των ακολουθιών δοκιμής. / The continual reduction of digital systems’ size in combination to the increase of their complexity, leads to the need of reliability. Consequently it is necessary to apply testing techniques in order to ensure the right functionality. The ways to apply the testing in an in package circuit is the external (off-chip – total use of the external ATE), the BIST (Built-In Self Test – no use of ATE) and the embedded (use of external ATE in combination to embedded test structures). This diploma thesis focus in the embedded testing and particular in test set embedding. In this technique the test set is embodied in a larger state sequence of a test pattern generator circuit. In this diploma thesis we suggest a new method of embedded testing which uses the reseeding of a LFSR. This method is used either in simple architectures with LFSR, or in multiphase architectures, always for circuits with multiple scan chains. In the multiphase architecture we take advantage of the sequence of bits that are driven by the various stages of a LFSR, which is used to generate test patterns, in order to embody the test set of the circuit under test. We present a new algorithm, which include four standards for the efficient selection of new seeds and states of the LFSR. Finally, we present a new method for test sequence length reduction. After that and in order to compare the results of the above method we implement a new technique, which has been suggested recently in the bibliography. This method is called REusing Scan chains for test Pattern decompressIoN (RESPIN) and its main characteristic is the test set embedding. According to this method, the decompression of test patterns is accomplished using the scan chains of another on-chip module, which is in idle state during the test. After a thorough comparison of these two techniques we conclude that the combination of the seed selection algorithm with the test sequence length reduction technique comprise an attractive solution and gives better results for the amount of data to be stored in the external ATE and for the test sequence length.

Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an Automated Test Equipment (ATE) and applying test patterns to test for different faults. With shrinking feature sizes, the complexity of the circuits on chip is increasing, which in turn increases the number of test patterns needed to test the chip comprehensively. This increases the test application time which further increases the cost of test, ultimately leading to increase in the cost per device. Furthermore, chips that fail during test need to be diagnosed to determine the cause of the failure so that the manufacturing process can be improved to increase the yield. With increase in the size and complexity of the circuits, diagnosis is becoming an even more challenging and time consuming process. Fast diagnosis of failing chips can help in reducing the ramp-up to the high volume manufacturing stage and thus reduce the time to market. To reduce the time needed for diagnosis, efficient diagnostic patterns have to be generated that can distinguish between several faults. However, in order to reduce the test application time, the total number of patterns should be minimized. We propose a technique for generating diagnostic patterns that are inherently compact. Experimental results show up to 73% reduction in the number of diagnostic patterns needed to distinguish all faults. Logic Built-in Self-Test (LBIST) is an alternative methodology for testing, wherein all components needed to test the chip are on the chip itself. This eliminates the need of expensive ATEs and allows for at-speed testing of chips. However, there is hardware overhead incurred in storing deterministic test patterns on chip and failing chips are hard to diagnose in this LBIST architecture due to limited observability. We propose a technique to reduce the number of patterns needed to be stored on chip and thus reduce the hardware overhead. We also propose a new LBIST architecture which increases the diagnosability in LBIST with a minimal hardware overhead. These two techniques overcome the disadvantages of LBIST and can make LBIST more popular solution for testing of chips. Modern designs may contain a large number of small embedded memories. Memory Built-in Self-Test (MBIST) is the conventional technique of testing memories, but it incurs hardware overhead. Using MBIST for small embedded memories is impractical as the hardware overhead would be significantly high. Test generation for such circuits is difficult because the fault effect needs to be propagated through the memory. We propose a new technique for testing of circuits with embedded memories. By using SMT solver, we model memory at a high level of abstraction using theory of array, while keeping the surrounding logic at gate level. This effectively converts the test generation problem into a combinational test generation problem and make test generation easier than the conventional techniques. / Ph. D.

In spite of the relative simple vegetation structure, the Grassland biome has surprisingly high species diversity. The Grassland biome is also the most transformed biome in South Africa, with cultivation having the largest impact. When croplands are abandoned, secondary succession leads to low diversity Hyparrhenia hirta dominated grassland. A combination of two seed mixtures, two seeding densities and two establishment methods was established in plots on a recently abandoned cropland at Suikerbosrand Nature Reserve to evaluate their effect on secondary succession. The rip plots, where more resources were available between the rip lines, have shown higher densities of relic weeds as well as local perennials, showing some progressive successional movement. However, Hyparrhenia hirta was one of the non-sown perennials increasing in the rip plots. Hyparrhenia invasion and relic weeds were best controlled in the plough plots. Although Hyparrhenia was successfully controlled in plough plots, no secondary succession occurred in these treatments. / Agriculture, Animal Health & Human Ecology / M. Tech. (Nature Conservation)

In spite of the relative simple vegetation structure, the Grassland biome has surprisingly high species diversity. The Grassland biome is also the most transformed biome in South Africa, with cultivation having the largest impact. When croplands are abandoned, secondary succession leads to low diversity Hyparrhenia hirta dominated grassland. A combination of two seed mixtures, two seeding densities and two establishment methods was established in plots on a recently abandoned cropland at Suikerbosrand Nature Reserve to evaluate their effect on secondary succession. The rip plots, where more resources were available between the rip lines, have shown higher densities of relic weeds as well as local perennials, showing some progressive successional movement. However, Hyparrhenia hirta was one of the non-sown perennials increasing in the rip plots. Hyparrhenia invasion and relic weeds were best controlled in the plough plots. Although Hyparrhenia was successfully controlled in plough plots, no secondary succession occurred in these treatments. / Agriculture, Animal Health and Human Ecology / M. Tech. (Nature Conservation)

Livestock (cattle and sheep) were examined as seed disseminators for reseeding degraded Intermountain rangelands. "Hycrest" crested wheatgrass [Agropyron desertorum (Fisch. ex Link) Schult. X A. cristatum (L.) Gaert.] seed was fed to yearling Holstein steers and Suffolk ewes. Dw1g was collected from each animal type and deposited on plots of high and low densities of an annual [cheatgrass (Bromus tectorum L.)] and perennial [squirreltail (Sitanion hystrix Nutt.)] grass species. The experiment evaluated the ability of the dung to suppress the resident vegetation, and the recruitment and establishment of Hycrest seedlings emerging from the dung. Sheep dung had little suppressive effect on resident vegetation and did not provide Hycrest with a favorable microsite for germination and establishment. Cattle dung provided favorable conditions for germination of Hycrest on all plots, but seedlings were unable to compete with either high or low densities of cheatgrass. Hycrest seedlings emerging from cattle dung were more successful in establishing on squirreltail plots, and most successful in establishing on the control plots (bare ground). Cheatgrass plants located near cattle and sheep dung benefited from an input of nutrients and a gapformation (with cattle dung), which translated into greater plant height, weight, and fecundity. The squirreltail plants did not show any noticable advantages gained from adjacent dung deposition. Even though cheatgrass was suppressed by cattle dung on the surface, its roots proliferated in the soil profile immediately under the cattle dungpat to levels equal to that found in other areas within the plots.

With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate external test equipment, enables the application of a large number of random tests, and allows for at-speed testing. The main problem with LBIST is suboptimal fault coverage achievable with random vectors. LFSR reseeding is used to increase the coverage. However, to achieve satisfactory coverage, one often needs a large number of seeds. Computing a small number of seeds for LBIST reseeding still remains a tremendous challenge, since the vectors needed to detect all faults may be spread across the huge LFSR vector space. In this work, we propose new methods to enable the computation of a small number of LFSR seeds to cover all stuck-at faults as a first-order satisfiability problem involving extended theories. We present a technique based on SMT (Satisfiability Modulo Theories) with the theory of bit-vectors to combine the tasks of test-generation and seed computation. We describe a seed reduction flow which is based on the `chaining' of faults instead of pre-computed vectors. We experimentally demonstrate that our method can produce very small sets of seeds for complete stuck-at fault coverage. Additionally, we present methods for inserting test-points to enhance the testability of a circuit in such a way as to allow even further reduction in the number of seeds. / Master of Science

Η μεταπτυχιακή αυτή εργασία μπορεί να χωριστεί σε δύο λογικά μέρη (Μέρος Α’ και Μέρος Β’). Το πρώτο μέρος αφορά τον έλεγχο ορθής λειτουργίας ψηφιακών κυκλωμάτων χρησιμοποιώντας το μοντέλο των Μεταβατικών (Transient) σφαλμάτων και πιο συγκεκριμένα περιλαμβάνει την μελέτη για το μοντέλο, τρόπο λειτουργίας και την υλοποίηση ενός Εξομοιωτή Μεταβατικών Σφαλμάτων (Transition Faults Simulator). Ο εξομοιωτής σφαλμάτων αποτελεί το πιο σημαντικό μέρος της αλυσίδας εργαλείων που απαιτούνται για τον σχεδιασμό και εφαρμογή τεχνικών ελέγχου ορθής λειτουργίας και η ύπαρξη ενός τέτοιου εργαλείου επιτρέπει την μελέτη νέων τεχνικών ελέγχου κάνοντας χρήση του Μεταβατικού μοντέλου σφαλμάτων. Το δεύτερο μέρος της εργασίας συνοψίζει την μελέτη που πραγματοποιήθηκε για την δημιουργία ενός νέου αλγόριθμου επιλογής διανυσμάτων ελέγχου στην περίπτωση των Test Set Embedding τεχνικών ελέγχου. Ο αλγόριθμος επιτυγχάνει σημαντικές μειώσεις τόσο στον όγκο των απαιτούμενων δεδομένων που είναι απαραίτητο να αποθηκευτούν για την αναπαραγωγή του ελέγχου, σε σχέση με τις κλασικές προσεγγίσεις ελέγχου, όσο και στο μήκος των απαιτούμενων ακολουθιών ελέγχου που εφαρμόζονται στο υπό-έλεγχο κύκλωμα σε σχέση με προγενέστερους Test Set Embedding αλγορίθμους. Στο τέλος του μέρους Β’ προτείνεται μία αρχιτεκτονική για την υλοποίηση του αλγόριθμου σε Built-In Self-Test περιβάλλον ελέγχου ορθής λειτουργίας ακολουθούμενη από την εκτίμηση της απόδοσης αυτής και σύγκριση της με την καλύτερη ως τώρα προτεινόμενη αρχιτεκτονική που υπάρχει στην βιβλιογραφία (Βλέπε Παράρτημα Α). / The thesis consists of two basic parts that apply in the field of VLSI testing of integrated circuits. The first one concludes the work that has been done in the field of VLSI testing using the Transient Fault model and more specifically, analyzes the model and the implementation of a Transition Fault Simulator. The transient fault model moves beyond the scope of the simple stuck-at fault model that is mainly used in the literature, by introducing the concept of time and therefore enables the testing techniques to be more precise and closer to reality. Furthermore, a fault simulator is probably the most important part of the tool chain that is required for the design, implementation and study of vlsi testing techniques and therefore having such a tool available, enables the study of new testing techniques using the transient fault model. The second part of the thesis summaries the study that took place for a new technique that reduces the test sequences of reseeding-based schemes in the case of Test Set Embedding testing techniques. The proposed algorithm features significant reductions in both the volumes of test data that are required to be stored for the precise regeneration of the test sequences, and the length of test vector sequences that are applied on the circuit under test, in comparison to the classical proposed test techniques that are available in the literature. In addition to the algorithm, a low hardware overhead architecture for implementing the algorithm in Built-in Self-Test environment is presented for which the imposed hardware overhead is confined to just one extra bit per seed, plus one, very small, extra counter in the scheme’s control logic. In the end of the second part, the proposed architecture is compared with the best so far proposed architecture available in the literature (see Appendix A)