Pre-silicon verification is an essential part of integrated circuit design to capture functional design errors. Complex simulation, emulation and formal verification tools are used in a virtual environment before the device is manufactured in silicon. However, as the design complexity increases and the design cycle becomes shorter for fast time-to-market, design errors are more likely to escape from the pre-silicon verification and functional bugs are found during the actual operation. Since manufacturing test primarily focuses on the physical defects, post-silicon validation is the final gatekeeper to capture these escaped design bugs. Consequently, post-silicon validation has become a critical path in shortening the development cycle of System-On-Chip(SoC) design. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for silicon debugging. Since a post-silicon validation operates on a fabricated chip, recording the values of each and every internal signals is not possible. Due to this limitation of post-silicon validation, acquiring the circuit's internal behavior with the limited available resources is a very challenging task in post-silicon validation. There are two main categories to expand the observability: trace and scan signal based approaches. Real time system response during silicon debug can be acquired using a trace signal based technique; however due to the limited space for the trace buffer, the selection of the trace signals is very critical in maximizing the observability of the internal states. The scan based approach provides high observability and requires no additional design overhead; however the designers cannot acquire the real time system response since the circuit operation has to be stopped to transfer the internal states. Recent research has shown that observability can be enhanced if trace and scan signals can be efficiently combined together, compared to the other debugging scenarios where only trace signals are monitored. This dissertation proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals using restorability values to maximize the observability of internal circuit states. In order to achieve this goal, we first introduce a technique to calculate restorability values accurately by considering both local and global connectivity of the circuit. Based on these restorability values, the dynamic trace signal selection algorithm is proposed to provide a higher number of restored states regardless of the incoming test vectors. Instead of using total restorability values, we separate 0 and 1 restorability values to differentiate the different circuit responses to the different incoming test vectors. Also, the two groups of trace signals can be selected dynamically based on the characteristics of the incoming test vectors to minimize the performance degradation with respect to the different incoming test vectors. Second, we propose a new algorithm to find the optimal number of trace signals, when trace and scan signals are combined together for better observability. Our technique utilizes restorability values and finds the optimal number of trace signals so that the remaining space of trace buffer can be utilized for the scan signals. Observability can be enhanced further with data compression technique. Since the entries of the dictionary are determined from the golden simulation, a high compression ratio can be achieved with little extra hardware overhead. Experimental results on benchmark circuits and a real industry design show that the proposed technique provides a higher number of restored states compared to the existing techniques. / text

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The Dual Failure Restorability (DFR) problems involve the design of network topology to be restorable in the event of single and dual failures scenarios. We developed new integer linear programming (ILP) models to optimally design mesh topology networks with various survivability schemes; span restoration, p-cycle, DSP and path restoration to achieve any specified level of dual failure restorability in the networks. The first variation of the ILP models applies specified dual failure restorability limit to each pair of spans in the network, and the second applies the limit to average dual failure restorability in the entire network. We used 137 test-case networks, consisting of four network families; 10-node, 12-node, 15-node, and 18-node network families. The results show that the capacity cost increases as the specified levels of dual failure restorability increases, and the relative increase in capacity cost in sparsely connected networks is much higher compare to densely connected networks. / Engineering Management