Pre-silicon verification is an essential part of integrated circuit design to capture functional design errors. Complex simulation, emulation and formal verification tools are used in a virtual environment before the device is manufactured in silicon. However, as the design complexity increases and the design cycle becomes shorter for fast time-to-market, design errors are more likely to escape from the pre-silicon verification and functional bugs are found during the actual operation. Since manufacturing test primarily focuses on the physical defects, post-silicon validation is the final gatekeeper to capture these escaped design bugs. Consequently, post-silicon validation has become a critical path in shortening the development cycle of System-On-Chip(SoC) design. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for silicon debugging. Since a post-silicon validation operates on a fabricated chip, recording the values of each and every internal signals is not possible. Due to this limitation of post-silicon validation, acquiring the circuit's internal behavior with the limited available resources is a very challenging task in post-silicon validation. There are two main categories to expand the observability: trace and scan signal based approaches. Real time system response during silicon debug can be acquired using a trace signal based technique; however due to the limited space for the trace buffer, the selection of the trace signals is very critical in maximizing the observability of the internal states. The scan based approach provides high observability and requires no additional design overhead; however the designers cannot acquire the real time system response since the circuit operation has to be stopped to transfer the internal states. Recent research has shown that observability can be enhanced if trace and scan signals can be efficiently combined together, compared to the other debugging scenarios where only trace signals are monitored. This dissertation proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals using restorability values to maximize the observability of internal circuit states. In order to achieve this goal, we first introduce a technique to calculate restorability values accurately by considering both local and global connectivity of the circuit. Based on these restorability values, the dynamic trace signal selection algorithm is proposed to provide a higher number of restored states regardless of the incoming test vectors. Instead of using total restorability values, we separate 0 and 1 restorability values to differentiate the different circuit responses to the different incoming test vectors. Also, the two groups of trace signals can be selected dynamically based on the characteristics of the incoming test vectors to minimize the performance degradation with respect to the different incoming test vectors. Second, we propose a new algorithm to find the optimal number of trace signals, when trace and scan signals are combined together for better observability. Our technique utilizes restorability values and finds the optimal number of trace signals so that the remaining space of trace buffer can be utilized for the scan signals. Observability can be enhanced further with data compression technique. Since the entries of the dictionary are determined from the golden simulation, a high compression ratio can be achieved with little extra hardware overhead. Experimental results on benchmark circuits and a real industry design show that the proposed technique provides a higher number of restored states compared to the existing techniques. / text

Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based tests or design bugs missed during pre-silicon validation. Critical to the diagnosis engineer is the ability to observe as many relevant internal signal values as possible during debug. To do so, trace buffers have been proposed for enhancing the observability of internal signals during post-silicon debug. Trace Buffers are used to trace (record the values of) the internal signals in real-time when chip is in its normal operation. However, existing trace buffer architectures trace very few signals for a large number of cycles. Thus, even with a good subset of signals traced, one often still cannot restore all the relevant values in the circuit. In this work, we propose two different flexible trace buffer architectures that can restore the values for all signals by making the trace signals configurable. In addition, the buffer space can also be shared among different traced signals which makes the architectures highly flexible. As compared to conventional trace buffer architectures, the new architectures have comparable area overhead but offer the ability to restore all signals in the circuit. For cases of less than 100% restoration, the ability of circuit invariants to improve the signal restoration is explored. A promising direction for the future work is provided where targeted invariants may lead to better restoration scenario during post-silicon validation. / Master of Science

<p>The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process.</p><p>An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug.</p><p>Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation.</p><p>This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test.</p><p>Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored.</p><p>The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.</p>

Submitted by Amauri Alves (amauri.alves@ufv.br) on 2016-02-12T13:56:54Z No. of bitstreams: 1 texto completo.pdf: 1954226 bytes, checksum: 9ae13d3f843542097b6e3009a011d0ec (MD5) / Made available in DSpace on 2016-02-12T13:56:55Z (GMT). No. of bitstreams: 1 texto completo.pdf: 1954226 bytes, checksum: 9ae13d3f843542097b6e3009a011d0ec (MD5) Previous issue date: 2015-04-24 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / lguns erros só acontecem quando o circuito é executado em sua velocidade real, assim, projetistas utilizam técnicas de depuração pós- silício para monitorar o circuito e capturar erros que ocorrem somente depois de milhões de ciclos de clock. Esse processo se tornou essencial e consome em média 35% do tempo de ciclo de desenvolvimento de um Circuito Integrado Digital. Na depuração pós-silício a limitação de observabilidade é um problema desafiador, e para identificar a causa de um erro o projetista inclui uma infraestrutura para depuração. Na técnica Trace Buffer alguns valores de sinais são armazenadas em uma memória de rastreamento, extraídos e analisados. O tamanho da memória de rastreamento restringe o número de sinais que podem ser analisados. A escolha do conjunto de sinais é essencial, porém é realizada antes mesmo de qualquer identificação de erro no projeto. Para possibilitar o monitoramento de diversos conjuntos de sinais, na indústria é utilizado uma rede de interconexão com- posto por multiplexadores encadeados (Mux Tree), que permite o projetista monitorar um subconjunto de todos os sinais que podem ser explorados. A arquitetura dessa rede não permite a seleção de qualquer conjunto de sinais, uma vez que sinais que passam pelos mesmos multiplexadores não podem ser monitorados juntos. Nesse trabalho é proposto uma nova rede de interconexão baseada na tradicional rede Ômega. A rede proposta pode ser utilizada como um dispositivo de interconexão para conectar os sinais monitorados à memória de rastreamento. Nesse trabalho é demonstrado que a rede Ômega assimétrica proposta pode reduzir em 4,5 vezes a taxa de bloqueio, ao custo de aumentar em 21% a área, se comparado à rede de Mux Tree. A rede Ômega assimétrica pode ser gerada utilizando a ferramenta proposta nesse trabalho, Vericonn, que também é capaz de gerar em Verilog outras redes assimétricas como: Redes Mux Tree, Clos e Crossbars. / Current pre-silicon verification techniques can not guarantee error free designs for complex integrated circuits during their first fabrication. Some errors are only uncovered when the device is running at full clock speed, thus, designers use post-silicon debug techniques to monitor the device, capturing errors that occur only after millions of clock cycles. This process has become essential and on average consumes 35% of the Digital Integrated Circuit development cycle. Observability limitation is a challenging problem in post-silicon debug, so to identify the root cause of an error, designers include an infrastructure for debug. In Trace Buffer technique, some signal values are stored in a Trace Buffer memory, dumped, and then analyzed. The Trace Buffer memory size limits the number of signals that can be analyzed. Choosing the signal set is an essential step, but it must be done prior to the identification of any design errors. To enable the monitoring of many sets of signals, industry uses an interconnection network composed by pipelined multiplexers (Mux Trees) that allows designers to monitor a signal subset from all tapped signals. The architecture of this network does not allow any signal subset because signals passing through the same multiplexers can not be monitored together. In this work, we propose a novel asymmetric network, based on the traditional Omega Network. We propose to use this network as an interconnection fabric to connect the monitored signals to the trace buffer. We demonstrate that our Asymmetric Omega Network is 4.5 times more effective reducing the blocking rate at the cost of 21% area overhead compared to Mux Trees. The proposed network can be generated with our tool, Vericonn, which is also capable to create others asymmetric networks like: Mux Trees, Clos Networks and Crossbars in Verilog HDL.

The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process. An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug. Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation. This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test. Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored. The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.

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