This thesis examines the use of ripple correlation control as a maximum power point tracking algorithm with an interleaved SEPIC converter for use with a solar array. The suitability of existing topologies for use with photovoltaic applications and the tradeoffs involved are discussed. The advantages of interleaving in converters are examined and the benefits it provides to photovoltaic applications are discussed. An interleaved SEPIC converter operated in interleaved mode with a photovoltaic array is studied. The operation of ripple correlation control as a maximum power point tracking technique applied to the interleaved SEPIC converter is examined and simulations with results are presented. / text

abstract: Switching regulator has several advantages over linear regulator, but the drawback of switching regulator is ripple voltage on output. Previously people use LDO following a buck converter and multi-phase buck converter to reduce the output voltage ripple. However, these two solutions also have obvious drawbacks and limitations. In this thesis, a novel mixed signal adaptive ripple cancellation technique is presented. The idea is to generate an artificial ripple current with the same amplitude as inductor current ripple but opposite phase that has high linearity tracking behavior. To generate the artificial triangular current, duty cycle information and inductor current ripple amplitude information are needed. By sensing switching node SW, the duty cycle information can be obtained; by using feedback the amplitude of the artificial ripple current can be regulated. The artificial ripple current cancels out the inductor current, and results in a very low ripple output current flowing to load. In top level simulation, 19.3dB ripple rejection can be achieved. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

Among PWM power conversion topologies, the single-switch forward topology is the one that has been most widely used for decades. Its popularity has been based on many factors, including its low cost, circuit simplicity and high efficiency. However, several issues need to be addressed when using the forward converter such as the core reset, the voltage spikes caused by the transformer leakage inductance, and the pulsating input current waveform. The transformer is driven in a unidirectional fashion in the forward converter; a tertiary forward converter (TFC) is an example of this. Therefore, the third winding and reset diode must be provided with an adequate period of reset time so that the flux can be fully reset by the end of each switching cycle to prevent core saturation. Also, due to the utilization of a transformer, leakage inductances cannot be avoided. The energy stored in the leakage inductance during current ramp-up is not transferred to the load, and is not recovered during its discharge phase. As a result, the VDS waveform has a voltage spike and undesirable high-frequency oscillation. Therefore, a higher voltage-rating switch should be used to reduce the risk of high-voltage breakdown. Although a switch with amply high voltage ratings is available, it would tend to have a higher on-resistance, RDS(ON), resulting in increased conduction losses. Moreover, selection of a switch with higher voltage ratings than necessary may needlessly increase the cost of the design. Usually an additional circuit such as a snubber circuit or a clamp circuit or the soft-switching technique is used to absorb these voltage spikes. Consequently, the leakage inductance is intentionally minimized in the PWM power conversion technique so that it will not degrade the circuit performance. In contrast, the leakage inductance of the transformer may enhance rather than detract from circuit performance with a resonant power conversion technique. To date, however, no single-switch forward converter has been claimed to be able to enhance the converter performance with the PWM power conversion technique by utilizing the leakage inductance. Therefore, research on the utilization of the transformer leakage inductance in the PWM forward converter is needed. Two techniques, input current ripple reduction and an embedded filter, are proposed to enhance the performance of forward converter using the PWM technique. By inserting a capacitor between two primary windings of the TFC, an input current ripple reduction technique is proposed and a forward converter with ripple reduction (FRR) is presented in this research work. Because the voltage of the capacitor is clamped to input voltage, the capacitor becomes a second voltage source to share part of the load current. As a result, the input current ripple is reduced. Moreover, the capacitor voltage is clamped both at the static and dynamic states; thus the excessive voltage stress on the main switch S1 of the FAC during low-line to high-line step transient is eliminated. Furthermore, without an external LC filter, the EMI noise levels can be further reduced as a result of the embedded notch filter formed by the transformer leakage inductance and clamp capacitor if the notch frequency is designed to be the same as the switching frequency. With the help of the clamp capacitor, therefore, the leakage inductance can enhance rather than detract from the converter performance. The input current ripple can be reduced further by employing the proposed techniques. Two sets of the clamp capacitors and the leakage inductances are utilized, and the current ripple can even be cancelled if the condition is met. Consequently, the input current becomes a non-pulsating waveform and a forward converter with ripple cancellation (FRC) is presented. Moreover, without an external LC filter, the EMI noise levels can be further attenuated as a result of the embedded low-pass filter formed by the transformer leakage inductances and clamp capacitors. Again, the leakage inductance can enhance the converter performance just as the resonant converter does. In addition to providing the analysis and design procedure, this work verifies the performance of the presented converters, the FRR and the FRC, by the experimental results. By employing the proposed techniques, eight new topologies have been extended for different power conversion applications. Each member of the FRR and the FRC families is able to enhance the converter performance, in ways such as the elimination of the voltage spikes on the main switch without a snubber circuit and the improvement of the EMI performance with small filter components. Consequently, the cost can be reduced and the space of the converter can be saved. / Ph. D.

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.