nÃo hà / The latest technologies of integrated circuit manufacturing allow billions of transistors to be arranged on a single chip, enabling us to implement a complex parallel system, which requires a communications architecture with high scalability and high degree of parallelism, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations, which increases the quantity of faults in circuit manufacturing and at runtime. Therefore, it is essential to provide a method for fault recovery that would enable the NoC to operate in the presence of faults and still ensure deadlock-free routing. The preprocessing of the most probable fault scenarios allows us to anticipate the calculation of deadlock-free routing, reducing the time that is necessary to interrupt the system during a fault occurrence. This work proposes a technique that employs the preprocessing of fault scenarios based on forecasting fault tendencies, which is performed with a fault threshold circuit operating in agreement with high-level software. The technique encompasses methods for dissimilarity analysis of scenarios based on cross-correlation measurements of fault link matrices, which allow us to define a reduced and efficient set of fault coverage scenarios. Experimental results employing RTL simulation with synthetic traffic prove the quality of the analytic metrics that are used to select the preprocessed scenarios. Furthermore, the experiments show the efficacy and efficiency of the proposed dissimilarity methods, quantifying the latency penalization when using the coverage scenarios approach. / As Ãltimas tecnologias de fabricaÃÃo de circuitos integrados habilitam bilhÃes de transistores a serem postos em um Ãnico chip, permitindo implementar um sistema paralelo complexo, o qual requer uma arquitetura de comunicaÃÃo que tenha grande escalabilidade e alto grau de paralelismo, tal como uma rede intrachip, em inglÃs, Network-on-Chip (NoC). Estas tecnologias estÃo muito prÃximas de limitaÃÃes fÃsicas, aumentando a quantidade de falhas na fabricaÃÃo dos circuitos e em tempo de operaÃÃo. Portanto, à essencial fornecer um mÃtodo para recuperaÃÃo de falha que permita a NoC operar na presenÃa de falhas e ainda garantir roteamento livre de deadlock. O prÃ-processamento de cenÃrios de falha mais provÃveis permite antecipar o cÃlculo de rotas livres de deadlock, reduzindo o tempo necessÃrio para interromper o sistema durante a ocorrÃncia de uma falha. Esta tese propÃe uma tÃcnica que emprega o prÃ-processamento de cenÃrios de falha baseado na previsÃo de tendÃncia de falhas, a qual à realizada com um circuito de limiar de falha operando em conjunto com um software de alto nÃvel. A tÃcnica contempla anÃlises de mÃtodos de dissimilaridade de cenÃrios baseadas na correlaÃÃo cruzada de matrizes bidimensionais de conexÃes com falha, que permite definir um conjunto reduzido e eficiente de cenÃrios de cobertura de falhas. Resultados experimentais, empregando simulaÃÃo com precisÃo em nÃvel de ciclo e trÃfego sintÃtico, provam a qualidade das mÃtricas analÃticas usadas para selecionar os cenÃrios prÃ-processados. AlÃm do mais, os experimentos mostraram a eficÃcia e eficiÃncia dos mÃtodos de dissimilaridades propostos, quantificando a penalizaÃÃo de latÃncia no uso da abordagem de cenÃrios de cobertura.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.