SRAM-Based FPGAs provide valuable computation resources and reconfigurability; however, FPGA designs can fail during operation due to ionizing radiation. As an SRAM-based device, these FPGAs store operation-critical information in configuration RAM, or CRAM. Testing, through radiation tests, can be performed to prove the effectiveness of SEU mitigation techniques by comparing the SEU sensitivity of an FPGA design with and without the mitigation techniques applied. However, radiation testing is expensive and time-consuming. Another method for SEU sensitivity testing is through fault injection. This work describes a low-cost fault injection platform for evaluating the SEU sensitivity of an SRAM-based FPGA design by emulating faults in the device CRAM through partial reconfiguration. This fault injection platform, called the TURTLE, is designed to gather statistically significant amounts of fault injection data to test and validate SEU mitigation techniques for SRAM-based FPGAs. Across multiple fault injection campaigns, the TURTLE platform was used to inject more than 600 million faults to test SEU mitigation techniques, estimate design SEU sensitivity, and validate radiation test data through fault injection.

SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to evaluate the SEU sensitivity of an FPGA design. This work describes a low-cost easier-to-implement approach for evaluating the SEU sensitivity of an FPGA design. This approach uses additional logic resources on the same FPGA as the design under test to determine when the design has failed, or deviated from its specified behavior. Three SEU mitigation techniques were evaluated using this approach: triple modular redundancy (TMR), configuration scrubbing, and user-memory scrubbing. Significant reduction in SEU sensitivity is demonstrated through fault injection and radiation testing. Two LEON3 processors operating in lockstep are compared against each other using on-chip error detection logic on the same FPGA. The design SEU sensitivity is reduced by 27x when TMR and configuration scrubbing are applied, and by approximately 50x when TMR, configuration scrubbing, and user-memory scrubbing are applied together. Using this approach, an SEU sensitivity comparison is made of designs implemented on both an Altera Stratix V FPGA and a Xilinx Kintex 7 FPGA. Several instances of a finite state machine are compared against each other and a set of golden output vectors, all on the same FPGA. Instances of an AES cryptography core are chained together and the output of two chains are compared using on-chip error detection. Fault injection and neutron radiation testing reveal several similarities between the two FPGA architectures. SEU mitigation techniques reduce the SEU sensitivity of the two designs between 4x and 728x. Protecting on-chip functional error detection logic with TMR and duplication with compare (DWC) is compared. Fault injection results suggest that it is more favorable to protect on-chip functional error detection logic with DWC than it is to protect it with TMR for error detection.