This dissertation presents a novel technique called duplicate with choose (DWCh) which is a modification of the fault detection technique duplicate with compare (DWC). DWCh adds a smart decider block to DWC that monitors the duplicated circuits and decides which circuit is fault free when a fault occurs. If chosen correctly, DWCh is able to mask faults at a lower cost than conventional techniques like TMR.This dissertation derives reliability expressions for DWCh showing that under ideal conditions its reliability exceeds the most commonly used fault masking technique for spacecraft, triple modular redundancy. For non-ideal conditions, DWCh provides a lower cost alternative than TMR but with lower reliability as well. Three types of DWCh smart deciders were developed for use with digital communications receivers. The first type used histograms as the statistical basis for the decider. The second type made use of moments for decision. The third type, although not generally applicable to other systems, used a signal common to communications receivers with excellent results. The communications receivers were subjected to hardware fault injection to gather datastreams affected by real world faults. The captured datastreams were used with Simulink models of the different deciders to quantify their performance and discover how a practical implementation of DWCh differs from the theoretical model. The increase in mean time to failure for DWCh when compared to simplex ranged from 20x to 130x depending on the specific smart decider tested.

Commercial off-the-shelf (COTS) microcontrollers can be useful for non-critical processing on spaceborne platforms. Many of these microprocessors are inexpensive and consume little power. However, the software running on these processors is vulnerable to radiation upsets, which can cause unpredictable program execution or corrupt data. Space missions cannot allow these errors to interrupt functionality or destroy gathered data. As a result, several techniques have been developed to reduce the effect of these upsets. Some proposed techniques involve altering the processor hardware, which is impossible for a COTS device. Alternately, the software running on the microcontroller can be modified to detect or correct data corruption. There have been several proposed approaches for software mitigation. Some take advantage of advanced architectural features, others modify software by hand, and still others focus their techniques on specific microarchitectures. However, these approaches do not consider the limited resources of microcontrollers and are difficult to use across multiple platforms. This thesis explores fully automated software-based mitigation to improve the reliability of microcontrollers and microcontroller software in a high radiation environment. Several difficulties associated with automating software protection in the compilation step are also discussed. Previous mitigation techniques are examined, resulting in the creation of COAST (COmpiler-Assisted Software fault Tolerance), a tool that automatically applies software protection techniques to user code. Hardened code has been verified by a fault injection campaign; the mean work to failure increased, on average, by 21.6x. When tested in a neutron beam, the neutron cross sections of programs decreased by an average of 23x, and the average mean work to failure increased by 5.7x.

In the presence of ionizing particles and other high-energy atomic sources, many electronic and computer systems fail. Single event upsets (SEUs) can be mitigated through hardware and/or software methods. Previous research at BYU has introduced COAST, a compiler-based tool that can automatically add software protection schemes to improve fault coverage of programs. This thesis will expand on the work already done with the COAST project by proving its effectiveness across multiple platforms and benchmarks. The ability to automatically add fault protection to arbitrary user programs will be very valuable for many application designers. The results presented herein show that mean work to failure (MWTF) of an application can increase from 1.2x – 36x when protected by COAST. In addition to the results based on bare metal applications, in this thesis we will show that it is both possible and profitable to protect a real-time operating system with COAST. We present experimental results which show that our protection scheme gives a 2x – 100x improvement in MWTF. We also present a fault injection framework that allows for rapid and reliable testing of multiple protection schemes across different benchmarks. The code setup used in this paper is publicly available. We make it public in the hope that it will be useful for others doing similar research to have a concrete starting point.

SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to evaluate the SEU sensitivity of an FPGA design. This work describes a low-cost easier-to-implement approach for evaluating the SEU sensitivity of an FPGA design. This approach uses additional logic resources on the same FPGA as the design under test to determine when the design has failed, or deviated from its specified behavior. Three SEU mitigation techniques were evaluated using this approach: triple modular redundancy (TMR), configuration scrubbing, and user-memory scrubbing. Significant reduction in SEU sensitivity is demonstrated through fault injection and radiation testing. Two LEON3 processors operating in lockstep are compared against each other using on-chip error detection logic on the same FPGA. The design SEU sensitivity is reduced by 27x when TMR and configuration scrubbing are applied, and by approximately 50x when TMR, configuration scrubbing, and user-memory scrubbing are applied together. Using this approach, an SEU sensitivity comparison is made of designs implemented on both an Altera Stratix V FPGA and a Xilinx Kintex 7 FPGA. Several instances of a finite state machine are compared against each other and a set of golden output vectors, all on the same FPGA. Instances of an AES cryptography core are chained together and the output of two chains are compared using on-chip error detection. Fault injection and neutron radiation testing reveal several similarities between the two FPGA architectures. SEU mitigation techniques reduce the SEU sensitivity of the two designs between 4x and 728x. Protecting on-chip functional error detection logic with TMR and duplication with compare (DWC) is compared. Fault injection results suggest that it is more favorable to protect on-chip functional error detection logic with DWC than it is to protect it with TMR for error detection.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-03-23T19:16:15Z No. of bitstreams: 2 GARDÊNIA MARINHO CORDEIRO - TESE PPGEQ 2016..pdf: 4354292 bytes, checksum: 1f9e0bf89dc6a2e1c64d5fa7f2e58a85 (MD5) ANEXO_TESE.pdf: 3069265 bytes, checksum: da63715d85442ba1e5c536dc5ebe121f (MD5) / Made available in DSpace on 2018-03-23T19:16:15Z (GMT). No. of bitstreams: 2 GARDÊNIA MARINHO CORDEIRO - TESE PPGEQ 2016..pdf: 4354292 bytes, checksum: 1f9e0bf89dc6a2e1c64d5fa7f2e58a85 (MD5) ANEXO_TESE.pdf: 3069265 bytes, checksum: da63715d85442ba1e5c536dc5ebe121f (MD5) Previous issue date: 2016-08-29 / Capes / A intensificação de processos através de colunas de parede dividida (DWC) e acoplamento térmico de duas colunas (TCS) são apontadas na literatura consultada como uma das alternativas mais promissoras para redução do consumo energético do processo de destilação. Especificamente ao processo de destilação extrativa, o uso destas configurações ainda é questionável e não consensual quanto ao seu potencial de redução de custos totais. Neste trabalho, a fim de avaliar rigorosamente a viabilidade de configurações TCS, três abordagens de redução de energia (otimização, integração térmica e acoplamento térmico) são analisadas e concatenadas de modo a reduzir o custo anual total (TAC) e consumo específico de energia (SEC). O uso de um procedimento de otimização baseado no teor de solvente, com garantia de solução ótima global foi eficiente na redução desses custos, uma vez que apresentou menores resultados (de SEC e TAC) em comparação com todos os fluxogramas da literatura analisados. A inclusão de uma integração térmica para pré-aquecer a alimentação do azeótropo com a corrente de reciclo mostrou-se competitiva com o uso do acoplamento térmico. Para estender a avaliação em configurações DWC, considerando a equivalência em termos de estágio de equilíbrio com TCS, é proposto uma estratégia sistemática para obtenção de uma configuração DWC otimizada, em termos operacionais e de design. Um comparativo rigoroso entre DWC e CS (também otimizada) foi realizado e demonstrou a influência do número de estágios das colunas no desempenho dessas configurações. Em relação aos custos energéticos, todas as DWC’s mostraram-se favoráveis, entretanto, o percentual de redução de carga térmica depende de qual CS tomou-se como referencial. Os melhores resultados de TAC foram obtidos para colunas com o número de estágios bem distintos em cada lado da parede, entretanto, essas colunas não superaram os sistemas convencionais otimizados. Economicamente, a decisão sobre o tipo de configuração mais viável para uma aplicação industrial pode ser tomada como base nas estratégias apresentadas, observando o trade-off entre a capacidade de redução energética das DWC’s e os custos do processo das configurações otimizadas. / The process intensification through dividing wall column (DWC) and thermal coupling of two columns (TCS) are noted in the literature consulted as one of the most promising alternatives to reduce energy consumption of the distillation process. Specifically by extractive distillation process, the use of these settings is still questionable and nonconsensual as to its potential to reduce total costs. In this work, in order to assess accurately the feasibility of TCS, three approaches of energy reduction (optimization, thermal and thermal coupling integration) are analysed and concatenated in order to reduce the total annual cost (TAC) and specific energy consumption (SEC). The use of an optimization procedure based on the solvent content, with guaranteed global optimal solution was effective in reducing these costs, since presented smaller results (SEC and TAC) compared to all studies of the literature examined. The inclusion of a thermal integration to preheat the azeotrope with the recycle proved to be competitive with the use of thermal coupling. To extend the assessment in DWC, considering the equivalence in terms of stage of equilibrium with TCS, proposed a systematic strategy for obtaining a DWC configuration optimized in terms of design and operational. A strict comparison between DWC and CS (optimized too) was performed and showed the influence of the number of stages of the columns in the performance of these configurations. In relation to energy costs, all the DWC's were favorable, however, the percentage of reduction of thermal load depends on which CS took as a reference. The best TAC’s results were obtained for columns with distinctive number of stages on each side of the wall, however, these columns do not have overcome the conventional systems optimized. Economically, the decision about the type of configuration more viable for an industrial application can be taken as the basis of the presented strategies, noting the trade-off between the ability of energy reduction of DWC's and the costs of the process of the optimized configurations.