Les techniques de localisation de défauts basées sur la stimulation laser restent aujourd'hui les techniques parmi les plus avancées qui existent. Elles permettent la stimulation thermique ou photoélectrique de façon très localisée sans contact physique. Les travaux dans ce mémoire sont consacrés au développement et à l’application de techniques d'analyse par faisceau laser impulsionnelles destinées à l'analyse des circuits intégrés. Le développement matériel et les investigations de méthodologies d'analyse ont été portés par la motivation du projet MADISON (Méthodes d’Analyse de Défaillances Innovantes par Stimulation Optique dyNamique), qui a pour but d'augmenter le taux de succès des analyses des circuits complexes VLSI par stimulation laser. L'utilisation de systèmes optiques très performants comprenant des sources laser impulsionnelles fibrées nous a permis d'explorer les capacités en termes d'analyse par stimulation laser photoélectrique impulsionelle. Une étude originale de l’étude du phénomène Latchup a montré une augmentation de la résolution latérale avec l'utilisation du processus d’absorption non linéaire. / The fault location based on laser stimulation are now among the most advanced available techniques. They allow thermal or photoelectric stimulation localized without physical contact.This Ph.D works was devoted to the development and application of techniques using pulsed laser for integrated circuits’ analyses.Material development and investigation of analysis methodologies have been held by the motivation of the MADISON project (Methods of Analysis of Failures by Innovative Dynamic Optical Stimulation), which aims to increase the success rate analysis of complex circuits VLSI by laser stimulation.We used high-performance optical systems including fibered pulsed laser sources to explore the capabilities in terms of analysis by photoelectric laser stimulation. An original study of the Latchup phenomenon showed an improving lateral resolution by using nonlinear absorption process.

Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. These tests were specifically designed to discover system susceptibilities, and effective mechanisms for upset detection, recovery, and recovery detection. Test results reveal that the Aurora protocol serves as an effective basis for simple point-to-point communication for space-based systems but that some additional logic is necessary for high reliability. Particularly, additional upset detection and recovery mechanisms are necessary as well as additional status indicators. These additions are minimal, however, and not all are necessary depending on system requirements. The most susceptible part of the MGT system is the MGT tile components on the RX data path. Upsets to these components most often results in data corruption only and do not affect system operation or disrupt the communication link. Most other upsets which do disrupt normal system operation can be recovered automatically by the Aurora protocol with built-in mechanisms. Only 1% of observed events in testing required additional recovery mechanisms not supplied by Aurora. In addition to test data results, this work also provides suggestions for system designers based on various system requirements and a proposed MGT system design based on the Aurora protocol. The proposed system serves as an example to illustrate how test data can be used to guide the system design and determine system availability. With this knowledge designers are able to build reliable MGT systems for a variety of space-based systems.

This work has extended an existing Aurora protocol for high-speed serial I/O between FPGAs to provide greater fault recovery in the presence of high-energy radiation. To improve on the Aurora protocol, additional resets that affect larger portions of the system were used. Detection for additional error modes that occurred but were not detected by the Aurora protocol was designed. Radiation testing was performed on the Aurora protocol with the additional mitigation hardware. The test gathered large amounts of data on the various error modes of the Aurora protocol and how the additional mitigation circuitry affected the system. The test results showed that the addition of the recovery circuitry greatly enhanced the Aurora protocol's ability to recover from errors. The recovery circuit recovered from all but 0.01% of errors that the Aurora protocol could not. The recovery circuit further increased the availability of the transmission link by proactively applying resets at much shorter intervals than used in previous testing. This quick recovery caused the recovery mechanism to fix some errors that may have recovered automatically with enough time. However, the system still showed an increase in performance, and unrecoverable errors were reduced 100x. The estimated unrecoverable error rate of the system is 5.9E-07 in geosynchronous orbit. The bit error rate of the enhanced system was 8.47754E-015, an order of magnitude improvement.

Commercial off-the-shelf (COTS) microcontrollers can be useful for non-critical processing on spaceborne platforms. Many of these microprocessors are inexpensive and consume little power. However, the software running on these processors is vulnerable to radiation upsets, which can cause unpredictable program execution or corrupt data. Space missions cannot allow these errors to interrupt functionality or destroy gathered data. As a result, several techniques have been developed to reduce the effect of these upsets. Some proposed techniques involve altering the processor hardware, which is impossible for a COTS device. Alternately, the software running on the microcontroller can be modified to detect or correct data corruption. There have been several proposed approaches for software mitigation. Some take advantage of advanced architectural features, others modify software by hand, and still others focus their techniques on specific microarchitectures. However, these approaches do not consider the limited resources of microcontrollers and are difficult to use across multiple platforms. This thesis explores fully automated software-based mitigation to improve the reliability of microcontrollers and microcontroller software in a high radiation environment. Several difficulties associated with automating software protection in the compilation step are also discussed. Previous mitigation techniques are examined, resulting in the creation of COAST (COmpiler-Assisted Software fault Tolerance), a tool that automatically applies software protection techniques to user code. Hardened code has been verified by a fault injection campaign; the mean work to failure increased, on average, by 21.6x. When tested in a neutron beam, the neutron cross sections of programs decreased by an average of 23x, and the average mean work to failure increased by 5.7x.

In the presence of ionizing particles and other high-energy atomic sources, many electronic and computer systems fail. Single event upsets (SEUs) can be mitigated through hardware and/or software methods. Previous research at BYU has introduced COAST, a compiler-based tool that can automatically add software protection schemes to improve fault coverage of programs. This thesis will expand on the work already done with the COAST project by proving its effectiveness across multiple platforms and benchmarks. The ability to automatically add fault protection to arbitrary user programs will be very valuable for many application designers. The results presented herein show that mean work to failure (MWTF) of an application can increase from 1.2x – 36x when protected by COAST. In addition to the results based on bare metal applications, in this thesis we will show that it is both possible and profitable to protect a real-time operating system with COAST. We present experimental results which show that our protection scheme gives a 2x – 100x improvement in MWTF. We also present a fault injection framework that allows for rapid and reliable testing of multiple protection schemes across different benchmarks. The code setup used in this paper is publicly available. We make it public in the hope that it will be useful for others doing similar research to have a concrete starting point.

Methods for testing commercial off-the-shelf (COTS) digital devices at varying levels of complexity is presented and discussed as well as the results for testing a COTS SRAM, FRAM, and SoC using these methodologies in a pulsed dose rate environment at Little Mountain Test Facility (LMTF) and neutron testing at Los Alamos Neutron Science Center (LANSCE). Investigations at LMTF revealed a dependence in all three devices on the integrated dose of a single pulse of radiation, implying that the duration of radiation plays a significant role in the response. The test infrastructure necessary to dynamically access an FRAM at LMTF and time the access with the pulse of radiation allowed for the discovery of a new FRAM failure mode where an entire word of the FRAM becomes corrupted as well as selecting between two different failure modes based on the timing of the pulse. A novel component-based testing methodology for testing complicated SoCs is presented and used to report on the cross-sections of several components on the Xilinx MPSoC, including its DMA which has not previously been reported.

FPGAs are frequently used in network systems to provide the performance and flexibility that is required of modern computer networks while allowing network vendors to bring products to market quickly. Like all electronic devices, FPGAs are vulnerable to ionizing radiation which can cause applications operating on an FPGA to fail. These low-level failures can have a wide range of negative effects on the performance of a network system. As computer networks play a larger role in modern society, it becomes increasingly important that these soft errors are addressed in the design of network systems.This work presents a framework for testing the soft-error reliability of FPGA-based networking systems. The framework consists of the NetFPGA development board, a custom traffic generator, and a custom high-speed JTAG configuration device. The NetFPGA development board is versatile and can be used to implement a wide range of network applications. The traffic generator is used to exercise the network system on the NetFPGA and to determine the health of that system. The JTAG configuration device is used to manage reliability experiments, to perform fault injection into the FPGA, and to monitor the NetFPGA during radiation tests.This thesis includes soft-error reliability tests that were performed on an Ethernet switch network system. Using both fault injection and accelerate radiation testing, the soft error sensitivity of the Ethernet switch was measured. The Ethernet switch design was then mitigated using triple module redundancy and duplication with compare. These mitigated designs were also tested and compared against the baseline design. Radiation testing shows that TMR provides a 5.05x improvement in reliability over the baseline design. DWC provides a 5.22x improvement in detectability over the baseline design without reducing the reliability of the system.

Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's configuration memory utilizing mechanisms such as Error Correction Codes (ECCs), Cyclic Redundancy Checks (CRCs), a protected golden file, and partial reconfiguration to detect and correct upset memory bits. This work presents improved Xilinx 7-Series configuration scrubbing architectures that achieve minimal hardware footprints, competitive performance metrics, and robust detection and correction capabilities. The two principal scrubbing architectures presented in this work are the readback and hybrid scrubbers which detect and correct Single Bit Upsets (SBUs) and Multi-Bit Upsets (MBUs). Harnessing the performance advantages granted by the 7-Series internal Readback CRC scan, a hybrid scrubber built in software for the Zynq XZC07020 FPGA has been measured to correct SBUs in 8.024 ms, even-numbered MBUs in 13.38 ms, and odd-numbered MBUs in 21.40 ms. It can also perform a full readback scrub of the entire device in under two seconds. These scrubbing architectures were validated in radiation beam tests, where one of the architectures corrected MBUs as large as sixteen bits in a single frame.

The Large Hadron Collider at CERN is scheduled to undergo upgrades in 2026-2028 to significantly increase its luminosity. These upgrades, while providing the experiments with a higher collision rate, pose a number of challenges to the design of the hardware and software in the detectors. The Tile Calorimeter (a scintillating sampling calorimeter read out by photomultiplier tubes) at the ATLAS experiment will have its read-out electronics completely replaced to enable performance and reliability improvements.  Advances in electronics, new requirements due to the luminosity upgrade as well as lessons learned from the current readout scheme drove development with the goals to partition the readout into small independent units with full granularity readout and a robust mitigation strategy for radiation induced errors. To verify the functionality of the new system while retaining backward compatibility a "Demonstrator'' has been developed to emulate the current functionality while using new and improved hardware. The board responsible for managing digitized calorimeter data and communicating with the off-detector electronics, called the DaughterBoard, is the main focus of this thesis. It has two electrically isolated sides for redundancy where each side consists of voltage regulators, two optical transceivers, a GigaBit transceiver chip (for clocking and configuration) and a Kintex FPGA for data processing. In addition to data management and transmission, the FPGA (and every other component) needs to be able to withstand the effects of radiation both in terms of total dose (ionization and displacement damage) and due to single event effects. The DaughterBoard was developed with this in mind and has undergone several radiation tests during its development to verify reliability and fault tolerance. / CERN

Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the circuit's netlist and how the circuit is placed and routed on the FPGA. TMR with repair showed a neutron cross-section improvement of 100x while the best mitigation technique proposed in this work showed an improvement of 700x.This work demonstrates both some causes behind single bit SEU failures for TMR circuits on FPGAs and mitigation techniques to address these failures. In addition to these findings, this work also shows that the majority of radiation failures in these circuits are caused by multiple cell upsets, laying the path for future work to further enhance the effectiveness of TMR on FPGAs.