Gustave Flaubert et Guy de Maupassant étaient des amis et des écrivains réalistes qui voulaient décrire la société en entier comme des artisans plutôt comme des artistes. En le faisant tous les deux utilisaient les habits des personnages dans leurs œuvres pour découvrir la société, la stratifictaion dans la société et les personnages des œuvres. Mais, malgré qu'ils veuillent travailler comme des artisans ils avaient des styles très précises et élaborés. L'approche sociocritique est la méthode pour comprendre; Comment les habits démasquent la position des personnages dans la société Comment les habits racontent l’histoire et la psychologie des personnages Comment les habits symbolisent les caractères dans un plus grand contexte littéraire / Gustave Flaubert and Guy de Maupassant were friends and realist authors who wanted to describe the totality of society as artisans rather than artists. In doing so both of them used  the way their characters dressed to discover society, the stratification in society and the characters in their literary work. However, in spite of their will to work as artisans they were stylistically prominent with styles precise and elaborated.From a socio-critical point of view this essay tries to understand: How the out-fit unveils the social position of the characters. How the out-fit unveils the story and psychology of the characters. How the out-fit symbolises the characters in a wider literary context. / Gustave Flaubert och Guy de Maupassant var vänner och realistiska författare som ville beskriva samhället i sin helhet som hantverkare snarare än konstnärer. När de gjorde det använde båda två personernas kläder för att avslöja samhället, klassuppdelningen i samhället och personernas psykologi i sina verk. Men, trots att de ville arbeta som hantverkare var båda stilistiskt framstående med varsin precis och genomarbetad stil.Från en sociokristisk synvinkel försöker denna uppsats förstå: Hur kläderna avslöjar personernas sociala ställning. Hur kläderna avslöjar personernas berättelse och psykologi. Hur kläderna symboliserar personerna i ett större litterärt sammanhang.

The SCMP processor presents a unique approach to processor design: integrating multiple processors, a network, and memory onto a single chip. The benefits to this design include a reduction in overhead incurred by synchronization, communication, and memory accesses. To properly determine its effectiveness, the SCMP architecture must be exercised under a wide variety of workloads, creating the need for a variety of applications. A compiler can relieve the time spent developing these applications by allowing the use of languages such as C and Fortran. However, compiler development is a research area in its own right, requiring extensive knowledge of the architecture to make good use of its resources. This thesis presents the design and implementation of a compiler for the SCMP architecture. The thesis includes an in-depth analysis of SCMP and the necessary design choices for an effective compiler using the SUIF and MachSUIF toolsets. Two optimizations passes are included in the discussion: partial redundancy elimination and instruction scheduling. While these optimizations are not specific to parallel computing, architectural considerations must still be made to properly implement the algorithms within the SCMP compiler. These optimizations yield an overall reduction in execution time of 15-36%. / Master of Science

Power gating is a technique commonly used for runtime leakage reduction in digital CMOS circuits. In microprocessors, power gating can be implemented by using sleep transistors to selectively deactivate circuit modules when they are idle during program execution. In this dissertation, a framework for power gating arithmetic functional units in embedded microprocessors with architecture and compiler support is proposed. During compile time, program regions are identified where one or more functional units are idle and sleep instructions are inserted into the code so that those units can be put to sleep during program execution. Subsequently, when their need is detected during the instruction decode stage, they are woken up with the help of hardware control signals. For a set of benchmarks from the MiBench suite, leakage energy savings of 27% and 31% are achieved (based on a 70 nm PTM model) in the functional units of a processor, modeled on the ARM architecture, with and without floating point units, respectively. Further, the impact of traditional performance-enhancing compiler optimizations on the amount of leakage savings obtained with this framework is studied through analysis and simulations. Based on the observations, a leakage-aware compilation flow is derived that improves the effectiveness of this framework. It is observed that, through the use of various compiler optimizations, an additional savings of around 15% and even up to 9X leakage energy savings in individual functional units is possible. Finally,in the context of multi-core processors supporting multithreading, three different microarchitectural techniques, for different multithreading schemes, are investigated for state-retentive power gating of register files. In an in-order core, when a thread gets blocked due to a memory stall, the corresponding register file can be placed in a low leakage state. When the memory stall gets resolved, the register file is activated so that it may be accessed again. The overhead due to wake-up latency is completely hidden in two of the schemes, while it is hidden for the most part in the third. Experimental results on multiprogrammed workloads comprised of SPEC 2000 integer benchmarks show that, in an 8-core processor executing 64 threads, the average leakage savings in the register files, modeled in FreePDK 45 nm MTCMOS technology, are 42% in coarse-grained multithreading, while they are between 7% and 8% in fine-grained and simultaneous multithreading. The contributions of this dissertation represent a significant advancement in the quest for reducing leakage energy consumption in microprocessors with minimal degradation in performance.