To allow faster and more reliable wireless communication a technique is to use multiple antennas in the transmitter and receiver. This technique is called MIMO. The usage of MIMO adds complexity to the receiver that must determine what the transmitter actually sent. This thesis focuses on hardware implementation suitable for an FPGA of a detection algorithm called SUMIS. A background to detection and SUMIS in particular is given as a theoretical aid for a better understanding of how an algorithm like this can be implemented. An introduction to hardware and digital design is also presented. A subset of the operations in the SUMIS algorithm such as matrix inversion and sum of logarithmic values are analyzed and suitable hardware architectures are presented. These operations are implemented in RTL hardware using VHDL targeted for an FPGA, Virtex-6 from Xilinx. The accuracy of the implemented operations is investigated showing promising results alongside of a presentation of the necessary resource usage. Finally other approaches to hardware implementation of detection algorithms are discussed and more suitable approaches for a future implementation of SUMIS are commented on. The key aspects are flexibility through software reprogrammability and area efficiency by designing a custom processor architecture.