To allow faster and more reliable wireless communication a technique is to use multiple antennas in the transmitter and receiver. This technique is called MIMO. The usage of MIMO adds complexity to the receiver that must determine what the transmitter actually sent. This thesis focuses on hardware implementation suitable for an FPGA of a detection algorithm called SUMIS. A background to detection and SUMIS in particular is given as a theoretical aid for a better understanding of how an algorithm like this can be implemented. An introduction to hardware and digital design is also presented. A subset of the operations in the SUMIS algorithm such as matrix inversion and sum of logarithmic values are analyzed and suitable hardware architectures are presented. These operations are implemented in RTL hardware using VHDL targeted for an FPGA, Virtex-6 from Xilinx. The accuracy of the implemented operations is investigated showing promising results alongside of a presentation of the necessary resource usage. Finally other approaches to hardware implementation of detection algorithms are discussed and more suitable approaches for a future implementation of SUMIS are commented on. The key aspects are flexibility through software reprogrammability and area efficiency by designing a custom processor architecture.

Non-linear continuous phase modulation has constant envelope and spectral efficiency, which are desirable for public safety communication systems where both bandwidth and power are limited. A practical design of an innovation based receiver for partial response CPM was recently developed for public safety applications. It is in the form of a linear predictive demodulator with a coefficient look up table. The demodulator shows great performance over multipath fading channels without channel equalization and promises a significant contribution to public safety communication. The work in this thesis is focussed on developing and analyzing modern techniques to improve the receiver performance while maintaining a feasible implementation complexity. Suitable soft output algorithms are incorporated into the demodulator allowing a subsequent convolutional decoder to perform soft decoding. By modifying the design criteria of the predictive demodulator and introducing a feedback loop, an iterative detection scheme is formed for the concatenated structure of demodulator, deinterleaver and decoder. Spatial diversity combining techniques are summarized and a very low complexity combining scheme is developed. It selects the best received sample sequence by considering the average energy of each sequence. In addition, the demodulator is extended to have dual coefficient look up tables supporting its detection by having parallel prediction processes and combining their results. This leads to an improvement in overall demodulator performance. A theoretical proof that only half the number of coefficients need to be stored in memory is also given. Matlab simulations on a Rayleigh fast fading multipath channel have shown that the proposed techniques significantly improve the overall detection accuracy. Each of them provides a good gain in signal to noise ratio or delay spread and when combined, a significant performance gain is achieved.

Ever increasing demand for higher data rates and better Quality of Service (QoS) for a growing number of users requires new transceiver algorithms and architectures to better exploit the available spectrum and to efficiently counter the impairments of the radio channel. Multiple-Input Multiple-Output (MIMO) communication systems employ multiple antennas at both transmitter and at the receiver to meet the requirements of next-generation wireless systems. It is a promising technology to provide increased data rates while not involving an equivalent increase in the spectral requirements. However, practical implementation of MIMO detectors poses a significant challenge and has been consistently identified as the major bottleneck for realizing the full potential that multiple antenna systems promise. Furthermore, in order to make judicious use of the available bandwidth, the baseband units have to dynamically adapt to different modes (modulation schemes, code rates etc) of operations. Flexibility and high throughput requirements often place conflicting demands on the Very Large Scale Integration (VLSI) system designer. The major focus of this dissertation is to present efficient VLSI architectures for configurable MIMO detectors that can serve as accelerators to enable the realization of next generation wireless devices feasible. Both, hard output and soft output detector architectures are considered.