Ce travail de thèse se concentre sur l'évaluation de la fiabilité des transistors à haute mobilité électronique (HEMT) AlGaN / GaN à grille ultra-courte sur substrat silicium dédiés aux applications de puissance à une fréquence supérieure à 40GHz. Il a été réalisé au sein des laboratoires IMS Bordeaux et IEMN Lille.Ce travail compare initialement les HEMT AlGaN / GaN réalisés par croissance MOCVD avec ceux obtenus par croissance MBE. En particulier, l'analyse électrique statique a permis d'étudier l'influence de la géométrie des dispositifs sur les performances des composants.Des tests de vieillissement accéléré ont été effectués pour évaluer la robustesse des transistors HEMTs en AlGaN/GaN à grille ultra-courte sur Si. Une méthodologie basée sur une séquence d'essais de vieillissement a été définie pour établir le diagnostic in-situ d’une dégradation statique et permanente et d’une dégradation qui se traduit par un transitoire de courant de drain au cours du chaque palier de la séquence de vieillissement. La valeur de la tension critique de dégradation à partir de laquelle le courant de drain commence à diminuer de façon significative dépend des conditions de polarisation du vieillissement, de la distance grille-drain et de la longueur de grille. De plus, l’aire de sécurité de fonctionnement de cette technologie a été déterminée. / This Ph.D. work focuses on the reliability assessment of ultra-short gate AlGaN/GaN high electron mobility transistor (HEMT) on silicon substrate dedicated to power applications at frequency above 40GHz. It was carried out within IMS Bordeaux and IEMN Lille laboratories.This work initially compares AlGaN/GaN HEMTs grown by MOCVD with those grown using MBE, through electrical characterization.In particular, the device geometry impact on the device performances has been studies by static electrical characterization.Step-stress experiments are performed to investigate reliability assessment of ultra-short gate AlGaN/GaN high electron mobility transistor (HEMT) on Si substrate. A methodology based on a sequence of step stress tests has been defined for in-situ diagnosis of a permanent degradation and of a degradation which is identified by a drain current transient occurring during each step of the ageing sequence . The same stress conditions were applied on HEMTs with different geometries. It is found no evolution of the drain current during non stressful steps. The value of the critical degradation voltage beyond which the stress drain current starts to decrease significantly is also found dependent on the stress bias conditions, the gate-drain distance and the gate length. Moreover, the safe operating area of this technology has been determined.

<p>We are in the midst of a technological revolution (popularly known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being equipped with hundreds of sensors that make them safer, homes are becoming smarter, industry yields are at an all-time high, and internet-of-things is a reality. This was largely possible due to the developments in communication, electronics, motor controls, robotics, cyber security, software, efficient power distribution, etc. One of the major propellants of the 4th Industrial revolution is the ever-expanding applications of power electronics devices. All electrical energy will be provided, handled, and consumed through power electronics devices in the near future. Therefore, the reliability of power electronics devices will be instrumental in driving future technological advances. </p> <p> </p> <p><br></p><p>A myriad of devices is categorized as power electronics devices, and in the heart of those devices are the transistors. Although Silicon-based transistors still dominate the power electronics market, a paradigm shift towards wide bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), beta-gallium oxide etc., is underway. However, realizing the full potential of these devices demands unconventional design, layout, and reliability. </p> <p> </p> <p>In this thesis, we try to establish a generalized model of reliability for power and logic transistors. We start by defining a comprehensive, substrate-, self-heating-, and reliability-aware safe operating area (SOA) that analytically establishes the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability before actual device fabrication. Then we take a deeper look into the reliability of individual transistors (a beta-gallium oxide transistor and a Silicon-based LDMOS), to test the predictions by the safe operating area, using both experiments and simulations. In the beta-gallium oxide transistor, we studied its implementation in a DC-DC voltage converter and concluded that the self-heating is a performance bottleneck and suggested approaches to alleviate it. For the LDMOS transistor, we investigated the hot carrier degradation (HCD) using experiments and simulations. We established that the HCD degradation kinetics is universal, and physics is the same as a classical transistor, despite a complicated geometry. Finally, we studied the correlation between HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to determine its lifetime. </p><p><br></p> <p> </p> <p>We have holistically analyzed the reliability of power transistors by extending the theories of logic transistors in this thesis. Therefore, this thesis takes us a step closer to a generalized reliability model for power transistors by developing a comprehensive and predictive model for the safe operating area, encompassing all sources of stresses (e.g., electrical, thermal, and radiation) it experiences during operation.</p>

ABSTRACT The Lateral Double-Diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOSFET or LDMOS) has made an enormous impact in the field of power electronics. Its integration, low cost, and power performance have made it the popular choice for power system on chips (SoC's). Over the years, much research has gone into ways of optimizing this crucial power device. Particularly, the safe operating area (SOA) has become a focus of research in order to allow a wide range of various bias schemes. More so, device ruggedness is an important factor in the usability of these devices as there are many circuits in which high current and voltage are present in a device. In this study, a conventional LDMOS is simulated using a 2-D device simulator. Two specific device enhancement techniques are implemented and analyzed, including a p+ bottom layer and an n-adaptive layer. The parasitic BJT of the LDMOS and its effect on SOA is investigated by using meaningful and in depth device cross-section analysis. The ruggedness of these devices are then considered and analyzed by means of an undamped inductive switching test (UIS). The purpose is to realize the relationship and the possible trade-offs between safe operating area enhancement and device ruggedness.

This work investigates the fundamental device limits related to operational voltage constraints and linearity in state-of-the-art silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in order to support the design of robust next-generation high-frequency transceivers. This objective requires a broad understanding of how much "usable" voltage exists compared to conventionally defined breakdown voltage specifications, so the role of avalanche-induced current-crowding (or "pinch-in") effects on transistor performance and reliability are carefully studied. Also, the effects of intermodulation distortion are examined at the transistor-level for new and better understanding of the limits and trade-offs associated with achieving enhanced dynamic range and linearity performance on existing and future SiGe HBT technology platforms. Based on these investigations, circuits designed for superior dynamic range performance are presented.