No description available.

Engineering faculty and administration at the Virginia Polytechnic Institute and State University (Virginia Tech) have recognized the importance of producing competent scientists and engineers to work in the vast semiconductor industry, especially in the emerging technologies of microelectronics, optoelectronics, and nanotechnology. For this reason, the development of an undergraduate microelectronics minor as well as a more rigorous graduate curriculum has been actively pursued for several years. This paper details the development of an advanced semiconductor processing laboratory course, which serves as a three credit hour capstone course. The course covers circuit layout, semiconductor fabrication, and electrical testing. The following steps were taken in order to accomplish this task: choosing and customizing a computer aided design (CAD) software package for device layout, pMOS process integration on the toolset in the cleanroom facilities at Virginia Tech, and the development of a laboratory manual. / Master of Science

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abstract: Perovskite solar cells are the next generation organic-inorganic hybrid technology and have achieved remarkable efficiencies comparable to Si-based conventional solar cells. Since their inception in 2009 with an efficiency of 3.9%, they have improved tremendously over the past decade and recently demonstrated 25.2% efficiency for single-junction devices. There are a few hurdles, however, that prevent this technology from realizing their full potential, such as stability and toxicity of the perovskites. Apart from solution processing in the fabrication of perovskites, precursor composition plays a major role in determining the quality of the thin film and its general properties. This work studies novel approaches for improving the efficiency and stability of the perovskite solar cells with minimized toxicity. The effect of excess Pb on photo-degradation in MAPbI3 perovskites in an inverted device architecture was studied with a focus on improving stability and efficiency. Precursor concentration with 5% excess Pb was found to be optimal for better efficiency and stability against photo-degradation. Further improvements in efficiency were made possible through the addition of Zirconium Acetylacetonate as a secondary electron buffer layer. A concentration of 1.5mg/ml was found to be optimal for demonstrating better efficiency and stability. Partial substitution of Pb with non-toxic Sr was also studied for improving the stability of inverted devices. Using acetate-derived precursors, 10% Sr was introduced into perovskites for improvements to the stability of the device. In another study, triple-cation perovskites with FAMACs cations were studied with doping different amounts of Phenyl Ethyl Ammonium (PEA) to induce a quasi 2D-3D structure for improved moisture stability. Doping the perovskite with 1.67% PEA was found to be best for improved morphology with fewer pinholes, which further resulted in better VOC and stability. A passivation effect for triple-cation perovskites was further proposed with the addition of a Guanidinium Iodide layer on the perovskite. Concentrations of 1mg/ml and 2mg/ml were demonstrated to be best for reducing defects and trap states and increasing the overall stability of the device. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2020

Vertical-cavity surface-emitting lasers (VCSELs) areattractive as potential inexpensive high-performance emittersfor fibre-optical communication systems. Their surface-normalemission together with the small dimensions are beneficial forlow-cost fabrication since it allows on-wafer testing,simplified packaging and effective fibre-coupling. Forhigh-speed data transmission up to hundreds of metres, 850-nmVCSELs are today the technology of choice. For higher bandwidthand longer distance networks, emission at long-wavelength(1.3-1.55 µm) is required. Long-wavelength VCSELs are,however, not available since no materials system offershigh-index-contrast distributed Bragg reflectors (DBRs) as wellas high-gain active regions at such wavelengths.High-performance DBRs may be built up from AlGaAs/GaAsmultilayers, but long wavelength quantum wells (QWs) are onlywell established in the InP system. Therefore, the bestperforming devices have relied on wafer-fusion betweenInP-based QWs and AlGaAs-DBRs. More recently, however, the mainefforts have been shifted towards all-epitaxial GaAs-baseddevices, employing 1.3-µm GaInNAs QWs. In this thesis, different processing technologies forlong-wavelength VCSELs are described. This includes a thoroughinvestigation of wafer-fusion between InP and GaAs regardingelectro-optical as well as metallurgical properties, and thedevelopment of a stable low-pressure process for the selectiveoxidation of AlAs. Optimised AlGaAs/GaAs DBRs were designed andfabricated. An important and striking observation from thatstudy is that n-type doping potentially is much moredetrimental to device performance than previously anticipated.These investigations were exploited in the realisation of twonew VCSEL designs. Near-room-temperature continuous-waveoperation of a single-fused 1.55-µm VCSEL was obtained.This demonstrated the potential of InGaAsP/InP DBRs inhigh-performance VCSELs, but also revealed a high sensitivityto self-heating. Further efforts were therefore directedtowards all-epitaxial GaAs-based structures. This resulted in ahigh-performance 1215-nm VCSEL with a highly strained InGaAssingle QW. This can be viewed as a basis for longer-wavelengthVCSELs, i.e., with an emission wavelength approaching 1300 nm,either by an extensive device detuning or with GaInNAs QWs. <b>Keywords</b>: VCSEL, vertical cavity laser, semiconductorlaser, long-wavelength, DBR, oxidation, wafer fusion, InGaAs,semiconductor processing

<p>Vertical-cavity surface-emitting lasers (VCSELs) areattractive as potential inexpensive high-performance emittersfor fibre-optical communication systems. Their surface-normalemission together with the small dimensions are beneficial forlow-cost fabrication since it allows on-wafer testing,simplified packaging and effective fibre-coupling. Forhigh-speed data transmission up to hundreds of metres, 850-nmVCSELs are today the technology of choice. For higher bandwidthand longer distance networks, emission at long-wavelength(1.3-1.55 µm) is required. Long-wavelength VCSELs are,however, not available since no materials system offershigh-index-contrast distributed Bragg reflectors (DBRs) as wellas high-gain active regions at such wavelengths.High-performance DBRs may be built up from AlGaAs/GaAsmultilayers, but long wavelength quantum wells (QWs) are onlywell established in the InP system. Therefore, the bestperforming devices have relied on wafer-fusion betweenInP-based QWs and AlGaAs-DBRs. More recently, however, the mainefforts have been shifted towards all-epitaxial GaAs-baseddevices, employing 1.3-µm GaInNAs QWs.</p><p>In this thesis, different processing technologies forlong-wavelength VCSELs are described. This includes a thoroughinvestigation of wafer-fusion between InP and GaAs regardingelectro-optical as well as metallurgical properties, and thedevelopment of a stable low-pressure process for the selectiveoxidation of AlAs. Optimised AlGaAs/GaAs DBRs were designed andfabricated. An important and striking observation from thatstudy is that n-type doping potentially is much moredetrimental to device performance than previously anticipated.These investigations were exploited in the realisation of twonew VCSEL designs. Near-room-temperature continuous-waveoperation of a single-fused 1.55-µm VCSEL was obtained.This demonstrated the potential of InGaAsP/InP DBRs inhigh-performance VCSELs, but also revealed a high sensitivityto self-heating. Further efforts were therefore directedtowards all-epitaxial GaAs-based structures. This resulted in ahigh-performance 1215-nm VCSEL with a highly strained InGaAssingle QW. This can be viewed as a basis for longer-wavelengthVCSELs, i.e., with an emission wavelength approaching 1300 nm,either by an extensive device detuning or with GaInNAs QWs.</p><p><b>Keywords</b>: VCSEL, vertical cavity laser, semiconductorlaser, long-wavelength, DBR, oxidation, wafer fusion, InGaAs,semiconductor processing</p>

Fluoride based chemical systems are widely used at various stages in microelectronic processing, particularly for wet cleaning and etching applications. Some examples include the use of semi aqueous fluoride (SAF) solutions in back end of line cleaning, the use of dilute HF solutions as etchants for SiO2 and HF-HNO3 or HF-H2O2 solutions as isotropic etchants for silicon. In this work, the use of fluoride based solutions for two applications relevant to semiconductor processing are considered.In the first part of the study, cleaning of post plasma etch residues generated during fabrication of copper damascene structures was investigated in semi aqueous fluoride (SAF) formulations based on dimethyl sulfoxide and ammonium fluoride. Formulations designed for residue removal should be able to remove the residue effectively, without causing critical dimension loss during the process cycle. A systematic evaluation of solution variables (solvent content and pH) was conducted and the extent of removal of model copper oxide films and selectivity over copper and carbon doped oxide (CDO) films were used as metrics to evaluate the formulations. Results of the study indicate that the presence of solvent is necessary to achieve reasonable etch selectivity over dielectric films. Additionally, a removal end point detection technique based on electrochemical impedance spectroscopy was developed, which could potentially help in the optimization of cleaning time with minimal dielectric loss. This method was applied to monitor the removal of copper oxide films as well as residue from patterned test structures.In the second part of the study, electrochemical formation of porous silicon films in hydrofluoric acid (HF) solutions was investigated, for potential applications in advanced packaging. Specifically, porous silicon formation in solution mixtures containing HF, acetic acid and peroxide, was studied. The effect of variables including current density, substrate resistivity, HF, acetic acid and peroxide concentration, on key porous film characteristics such as growth rate, porosity and microstructure, was explored. Addition of peroxide was found to significantly increase the porosity and growth rate of the film, as a result of enhanced chemical dissolution and films with porosities as high as 95% were obtained. Additionally, in solutions containing peroxide, a variety of microstructural features, such as nanopores, micron sized pores, truncated pyramidal structures and silicon needles were observed, under various fabrication conditions.

In the recent years, there has been a growing interest in micro- and nano-structured composite systems due to their wide use in microelectronics, optoelectronics, magneto-optical devices, high-density data storage, sensors, biomedical devices, and many other areas. Of particular interest is application in the integrated circuit (IC) industry. Here the need for miniaturization has led to new architectures that combine disparate technologies. This has been achieved through innovations in packaging technologies such as 3D integration for high interconnection density, low power, high data throughput, good signal integrity and reliability, and low cost. One of the key active manufacturing technologies for 3D integration is through silicon vias (TSVs), which involves etching of deep vias in a silicon substrate that are filled with an electrodeposited metal, and subsequent removal of excess metal by chemical mechanical planarization (CMP). Electrodeposition often results in undesired voids in the TSV metal fill as well as a thick overburden layer. These via plating defects can severely degrade interconnect properties and lead to variation in via resistance, electrically open vias, and trapped plating chemicals that present a reliability hazard. Thick overburden layers result in lengthy and expensive CMP processing. We are proposing a technique that pursues a viable method of depositing a high quality metal inside vias with true bottom-up filling, using an additive-free deposition solution. The mechanism is based on a novel concept of electrochemical oxidation of backside silicon that releases electrons, and subsequent chemical etching of silicon dioxide for regeneration of the surface. Electrons are transported through the bulk silicon to the interface of the via bottom and the deposition solution, where the metal ions accept these electrons and electrodeposit resulting in the bottom-up filling of the large aspect ratio vias. With regions outside the vias covered bydielectric, no metal electrodeposition should occur in these regions, which minimizes the metal CMP step and reduces the overall processing times and costs. Hence, inherent bottom-up filling is financially advantageous because it will eliminate a large portion of the metal overburden and associated planarization costs. Additive-free deposition is preferable from both lower production cost and quality management perspectives since it results in higher reliability of deposited metal. Our new bottom-up technique was initially examined and successfully demonstrated on blanket silicon wafers and shown to supply electrons to provide bottom-up filling advantage of through-hole plating and the depth tailorability of blind vias. In order to understand the driving mechanism and limits of this process, we have also conducted a fundamental study that investigated the effect of various process parameters on the characteristics of deposited Cu and Ni and established correlations between metal filling properties and various electrochemical and solution variables. A copper sulfate solution with temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of ~2.4 μm/min with good deposition uniformity. The importance of backside silicon oxidation and subsequent oxide etching on the kinetics of metal deposition on front side silicon has also been highlighted. Further, a process model was also developed to simulate the through silicon via copper filling process using conventional and contactless electrodeposition methods with no additives being used in the electrolyte solution. A series of electrochemical measurements were employed and integrated in the development of the comprehensive process simulator. The experimental data not only provided the necessary parameters for the model but also validated the simulation accuracy. From the simulation results, the “pinch-off” effect was observed for the additive-free conventional deposition process, which further causes partial filling and void formation. By contrast, a void-free filling with higher deposition rates was achieved by the use of the contactless technique. Moreover, experimental results of contactless electrodeposition on patterned wafers showed fast rate bottom-up filling (~3.3 μm/min) in vias of 4 μm diameter and 50 μm depth (aspect ratio = 12.5) without void formation and no copper overburden in the regions outside the vias. Efforts were also made to extend the use of the contactless technique to other applications such as synthesis of porous silicon, which is known to be an excellent material with fascinating physical and chemical properties. We were able to fabricate porous silicon with a morphological gradient using a novel design of the experimental cell. The resulted porous silicon layers show a large distribution in porosity, pore size and depth along the radius of the samples. Symmetrical arrangements were attributed to decreasing current density radially inward on the silicon surface exposed to surfactant containing HF based etchant solution. The formation mechanism as well as morphological properties and their dependence on different process parameters, such as HF concentration, solution pH, surfactant concentration, current density and wafer resistivity, has been investigated in detail. In the presence of surfactants, an increase in the distribution range of porosity, pore diameter and depth was observed by increasing HF concentration or lowering pH of the etchant solution, as the formation of pores was considered to be limited by the etch rates of silicon dioxide. Gradient porous silicon was also found to be successfully formulated both at high and low current densities. Interestingly, the morphological gradient was not developed when dimethyl sulfoxide (instead of surfactants) was used in etchant solution potentially due to limitations in the availability of oxidizing species at the silicon-etchant solution interface. In the last part of the dissertation, we have discussed the gradient bottom up filling of Cu in porous silicon substrates using the contactless electrochemical method. The radially symmetric current that gradually varied across the radius of the sample area was achieved by utilizing the modified cell design, which resulted in gradient filling in the vias. Effect of different deposition parameters such as applied current density, copper sulfate concentration and etching to deposition area ratio has been examined and discussed. Increasing the current density from 10 to 15 mA/cm2 resulted in bottom up deposition with less sharp gradients. Further, the study on the effect of copper sulfate concentration highlighted the importance of mass transfer in this process, as either bottom-up deposition or gradient filling could not be achieved at lower CuSO4 concentrations (0.1 and 0.25 M). Additionally, the filling gradient of deposited Cu was obtained with etching to deposition area ratio of 1.6 and 2.7, while a more uniform deposition was observed when the ratio was increased to 3.8. This suggested that the gradient filling may only be accomplished within a certain range of the etching to deposition area ratios.

No description available.

Particle contamination control is a critical issue for the semiconductor industry. In the near future, this industry will be concerned with the chemical identities of contaminant particles as small as 0.01 pm in size. Therefore, analytical techniques with both high chemical sensitivity and spatial resolution are required. Transmission electron microscopy (TEM) provides excellent spatial resolution and yields structural and compositional information. It is rarely used, however, due to the difficulty of sample preparation. The goals of this research are to promote the use of TEM as an ultrafine particle analysis tool by developing new sample preparation methods, and to exploit the new TEM techniques for analysis of particles in semiconductor processing fluids. A TEM methodology for the analysis of particulate contaminants in fluids with an elemental detectability limit as low as 0.1 part per trillion (ppt), and a particle concentration detectability limit as low as 1 particle/ml for particles greater than 0.2 pm was developed and successfully applied to the analysis of particles in HF, H202, de-ionized (DI) water, and on the surface of an electronic device. HF samples from three manufacturers were examined. For HF (B), the maximum particle concentration was 8.3 x 103 particles/ml. Both a viscous material and lath-shaped particles were observed. The Sb concentration was less than 0.6 part per billion (ppb). HF (C) was the cleanest. CaF2 and TiO2 particles were identified in HF (D). For H2 02, iron and tin oxides and hydroxides were identified. The maximum particle concentration was 990 particles/ml. The Sn and Fe concentrations were less than 0.3 ppb. Spherical and dendritic particles were observed. For DI water, spherical and dendritic particles (<2 particles/ml), and particles containing Fe or Si with concentrations less than 0.1 ppt were observed. Contaminants on an electronic device surface were also analyzed. Clusters of small particles were determined to be a mixture of aluminum oxides and aluminum silicates.