No description available.

Lau Wai Kwok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references. / Acknowledgement --- p.iv / Abstract --- p.v / Chapter Chapter 1 --- Introduction --- p.1-1 / Chapter 1.1 --- Perspective --- p.1-1 / Chapter 1.2 --- MEDICI - The Simulation Package --- p.1 -2 / Chapter 1.3 --- Overview --- p.1-3 / Chapter Chapter 2 --- The Emergence of SOI Devices --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Advantages of SOI Devices --- p.2-1 / Chapter 2.2.1 --- Reliability Improvement --- p.2-2 / Chapter 2.2.2 --- Total Isolation --- p.2-3 / Chapter 2.2.3 --- Improved Junction Structure --- p.2-4 / Chapter 2.2.4 --- Integrated Device Structure --- p.2-5 / Chapter 2.3 --- Categories of SOI Devices --- p.2-6 / Chapter 2.3.1 --- Thick Film SOI Devices --- p.2-7 / Chapter 2.3.2 --- Thin Film SOI Devices --- p.2-8 / Chapter 2.3.3 --- Medium Film SOI Devices --- p.2-8 / Chapter 2.4 --- Drawbacks of SOI Devices --- p.2-9 / Chapter 2.4.1 --- Floating Body Effects --- p.2-9 / Chapter 2.4.2 --- Parasitic Bipolar Effects --- p.2-11 / Chapter 2.4.3 --- Cost --- p.2-15 / Chapter 2.5 --- Manufacturing Methods --- p.2-16 / Chapter 2.5.1 --- Epitaxy-Based Method --- p.2-16 / Chapter 2.5.2 --- Recrystallization-Based Method --- p.2-18 / Chapter 2.5.3 --- Wafer Bonding Based Method --- p.2-19 / Chapter 2.5.4 --- Oxidation Based Method --- p.2-20 / Chapter 2.5.5 --- Implantation Based Method --- p.2-22 / Chapter 2.6 --- Future Trend --- p.2-22 / Chapter 2.7 --- The Quest for Silicon-On-Nitride Structure --- p.2-23 / Chapter Chapter 3 --- Description of Body-Contact SOI Structure --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Current Status of Body-Contact SOI Structure --- p.3-1 / Chapter 3.3 --- The Body-Contact SOI Structure to be studied --- p.3-4 / Chapter 3.4 --- Impact on Device Fabrication --- p.3-7 / Chapter 3.4.1 --- Fabrication of Conventional Bulk CMOS --- p.3-7 / Chapter 3.4.2 --- Fabrication of Conventional SOI CMOS --- p.3-8 / Chapter 3.4.3 --- Fabrication of BC SOI CMOS --- p.3-10 / Chapter Chapter 4 --- Device Simulations --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- MEDICI --- p.4-1 / Chapter 4.2.1 --- Basic Equations --- p.4-2 / Chapter 4.2.2 --- Solution Methods --- p.4-3 / Chapter 4.2.3 --- Initial Guess --- p.4-6 / Chapter 4.2.4 --- Grid Allocations --- p.4-7 / Chapter 4.2.5 --- Source File --- p.4-8 / Chapter 4.3 --- Structures for Simulations --- p.4-9 / Chapter 4.3.1 --- l.2μm NMOS Bulk (LDD) --- p.4-9 / Chapter 4.3.2 --- 1.2μm SOI(O) NMOS 1000/3500 NBC --- p.4-11 / Chapter 4.3.3 --- 1.2μm SOI(N) NMOS 1000/3500 NBC --- p.4-12 / Chapter 4.3.4 --- 1.2μm SOI(O) NMOS 1000/3500 WBC --- p.4-13 / Chapter 4.3.5 --- 1.2μm SOI(N) NMOS 1000/3500 WBC --- p.4-14 / Chapter 4.4 --- Summary --- p.4-14 / Chapter Chapter 5 --- Simulation Results --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Comparisons of Different Structures --- p.5-1 / Chapter 5.2.1 --- Impurity Profiles of Structures --- p.5-2 / Chapter 5.2.2 --- Body Effect --- p.5-10 / Chapter 5.2.3 --- Breakdown Voltage and Transistor Current Driving --- p.5-16 / Chapter 5.2.4 --- Transconductance and Mobility --- p.5-20 / Chapter 5.2.5 --- Subthreshold Swing --- p.5-23 / Chapter 5.3 --- Dependence on Key Structure Parameters --- p.5-29 / Chapter 5.3.1 --- Dependence on Insulator Thickness --- p.5-29 / Chapter 5.3.2 --- Dependence on Silicon Overlayer Thickness --- p.5-34 / Chapter 5.3.3 --- Dependence on Size of Body-Contact --- p.5-37 / Chapter 5.4 --- Summary --- p.5-40 / Chapter Chapter 6 --- Reduction of Latch-up Susceptibility --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Construction of a p-channel MOS Transistor --- p.6-2 / Chapter 6.2.1 --- Threshold Voltage and Body Effect --- p.6-3 / Chapter 6.2.2 --- I-V Characteristics --- p.6-3 / Chapter 6.2.3 --- Transconductance --- p.6-5 / Chapter 6.2.4 --- Subthreshold Swing --- p.6-5 / Chapter 6.3 --- Mechanism of Latch-up in CMOS --- p.6-6 / Chapter 6.4 --- Construction of a CMOS Invertor for Simulation --- p.6-10 / Chapter 6.5 --- Latch-up Susceptibility Dependence --- p.6-16 / Chapter 6.5.1 --- Dependence on Insulator Thickness --- p.6-16 / Chapter 6.5.2 --- Dependence on N-well Depth --- p.6-19 / Chapter 6.5.3 --- Dependence on Transistor Separation --- p.6-22 / Chapter 6.5.4 --- Dependence on Size of Body-Contact --- p.6-25 / Chapter 6.6 --- Summary --- p.6-28 / Chapter Chapter 7 --- Conclusions --- p.7-1 / Chapter 7.1 --- Summary --- p.7-1 / Chapter 7.2 --- Recommendation --- p.7-3 / Reference / Appendix A

Monitoring and diagnosis of the control system, though widely used in the chemical processing industry, is currently lacking in the semiconductor manufacturing industry. This work provides methods for performance assessment of the most commonly used control system in this industry, namely, run-to-run process control. First, an iterative solution method for the calculation of best achievable performance of the widely used run-to-run Exponentially Weighted Moving Average (EWMA) controller is derived. A normalized performance index is then defined based on the best achievable performance. The effect of model mismatch in the process gain and disturbance model parameter, delays, bias changes and nonlinearity in the process is then studied. The utility of the method under manufacturing conditions is tested by analyzing three processes from the semiconductor industry. Missing measurements due to delay are estimated using the disturbance model for the process. A minimum norm estimation method coupled with Tikhonov regularization is developed. Simulations are then carried out to investigate disturbance model mismatch, gain mismatch and different sampling rates. Next, the forward and backward Kalman filter are applied to obtain the missing values and compared with previous examples. Manufacturing data from three processes is then analyzed for different sampling rates. Existing methods are compared with a new method for state estimation in high-mix manufacturing. The new method is based on a random walk model for the context states. This approach is also combined with the recursive equations of the Kalman filter. The method is applied to an industrial exposure process by extending the random walk model into an integrated moving average model and weights used to give preference to the context that is more frequent. Finally, a performance metric is derived for PID controllers, when they are used to control nonlinear processes. Techniques to identify nonlinearity in a process are introduced and polynomial NARX models are proposed to represent a nonlinear process. A performance monitoring technique used for MIMO processes is then applied. Finally, the method is applied to an EWMA control case used before, a P/PI control case from literature and two cases from the semiconductor industry. / text

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published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / Chemistry / Doctoral / Doctor of Philosophy

The device optimization is a very important element in semiconductor technology advancement. Its objective is to find a design point for a semiconductor device so that the optimized design goal meets all specified constraints. As in other engineering fields, a nonlinear optimizer is often used for design optimization. One major drawback of using a nonlinear optimizer is that it can only partially explore the design space and return a local optimal solution. This dissertation provides an adaptive optimization design methodology to allow the designer to explore the design space and obtain a globally optimal solution. One key element of our method is to quickly compute the set of all feasible solutions, also called the acceptability region. We described a polytope-based representation for the acceptability region and an adaptive linearization technique for device performance model approximation. These efficiency enhancements have enabled significant speed-up in estimating acceptability regions and allow acceptability regions to be estimated for a larger class of device design tasks. Our linearization technique also provides an efficient mechanism to guarantee the global accuracy of the computed acceptability region. To visualize the acceptability region, we study the orthogonal projection of high-dimensional convex polytopes and propose an output sensitive algorithm for projecting polytopes into two dimensions.

自從2004年人們在實驗室上發現石墨烯以來，IV族二維半導體材料，例如石墨烯、硅烯等，由於其優異的電學、力學、光學、以及熱力學性質，受到學術界的廣泛關注。為了使IV族二維半導體材料得到廣泛引用，穩定地生長高質量的石墨烯、硅烯二維半導體材料以及透徹的理解石墨烯、硅烯二維半導體材料和襯底之間的界面特性成為至關重要的研究方向。本文對在銅表面用多環芳香烴形成石墨烯的生長機理以及石墨烯、硅烯和襯底之間的界面電子學特性進行了詳細的分析和研究。希望以此能對IV族二維半導體材料的廣泛應用具有促進作用，並且對合理的設計電子器件結構具有新的啟示。 / 首先，我們用密度泛函理論對在銅表面用多環芳香烴形成石墨烯的生長機理進行了研究。理論計算表明在銅表面多環芳香烴形成石墨烯的生長過程主要包括：（1）在銅表面的誘導下多環芳香烴脫氫，（2）這些已經脫氫的多環芳香烴在銅表面相互結合形成石墨烯。由於銅和碳的相互作用非常弱，所以在銅表面這些已經脫氫的多環芳香烴並不會進一步分解成更小的碳團簇或者單個的碳原子。因此多環芳香烴的空間幾何構型對於最終形成的石墨烯的質量以及最低成長溫度有至關重要的影響。提高生長溫度可以提升脫氫多環芳香烴的活性和熱運動性，從而提高最終生成的石墨烯的質量。六苯并苯由於具有和石墨烯相同的六重對稱性和晶格結構，所以其在低溫生長高質量石墨烯方面最具有優勢。 / 其次，我們就石墨烯和（0001）二氧化硅表面所組成的界面的電子學特性進行了研究。結果表明石墨烯在（0001）二氧化硅表面的電子學特性主要有二氧化硅表面的性質以及氫化程度決定。如果用末端為甲基的分子修飾（0001）二氧化硅表面，可以進一步減弱二氧化硅表面氧原子對石墨烯電子學特性的影響，從而提高在二氧化硅表面石墨烯的載流子遷移率。此外，當石墨烯物理吸附在二氧化硅表面上時，垂直於石墨烯和二氧化硅界面的外加電場可以調製石墨烯和二氧化硅表面的電荷轉移。這一效應可以增強雙層石墨烯之間的電場，從而有效改變雙層石墨烯的能帶結構。我們的結果有助於更好的地認識和理解石墨烯吸附在二氧化硅表面所表現的實驗現象。 / 基於以上兩個結論，我們用三亚苯合成了高質量的單層石墨烯，並對其在普通二氧化硅表面上以及十八烷基鏈三甲氧基硅烷所修飾的二氧化硅表面上，所體現出的不同電子學性質和散射機理進行了詳細研究。用三亚苯作為石墨烯的生長源可以避免傳統氣象化學沉積方法在初期成核過程中所產生的缺陷，從而得到高質量的石墨烯。電學測量表明，石墨烯在普通二氧化硅表面上的載流子遷移率約為5090 cm²V⁻¹s⁻¹。而在十八烷基鏈三甲氧基硅烷所修飾的二氧化硅表面上，其遷移率可以提高到大約9080 cm²V⁻¹s⁻¹。此外，通過這兩種不同結構的電子器件進行定量的分析和對比，我們發現在室溫下，普通二氧化硅表面上的石墨烯電子器件的平均自由程主要由電離雜質所引起的長程散射所決定，電離雜質散射源密度約為5.34×10¹¹ cm⁻²。而對於十八烷基鏈三甲氧基硅烷所修飾的二氧化硅表面上的石墨烯電子器件的平均自由程主要由甲基以及石墨烯中的缺陷和晶界所引起的共振散射所決定，共振散射源密度為9.77×10¹° cm⁻²。我們的研究結果有助於揭示通過界面修飾來提升石墨烯電子器件性能的內在原理。 / 最後， 我們對單層石墨烯和硅烯封裝在金剛石薄膜和硅薄膜結構的電子學性質，以及其隨壓強的變化，進行了系統的理論研究。結果表明，當單層石墨烯和硅烯封裝在金剛石薄膜和硅薄膜中時，通過改變壓強和堆疊結構，單層石墨烯和硅烯在狄拉克點處的能隙和電子有效質量可以被有效地調製。電子有效質量和壓強成正比。硅烯的能隙對於壓強的變化比石墨烯更加敏感。並且異質封裝結構比同質封裝結構更有利於調製石墨烯和硅烯在狄拉克點處的能隙和電子有效質量。利用封裝技術和改變壓強的方法，石墨烯和硅烯的蜂窩狀結構不會被破壞，所以其小的載流子有效質量和高的載流子遷移率將會保持。所以對於構造高性能的納米電子學器件，這種方法有明顯的應用前景。 / Group IV two Dimensional Semiconductor Materials, such as graphene, silicene and so on, composed of an atomically thin layer of carbon and silicon atoms arranged in a honeycomb lattice, have received considerable attention, as their extraordinary electronic, mechanical, optical, and thermal properties arise from their unique 2D energy dispersions, since their representive, graphene, experimentally discovered in 2004. Reliable fabrication of high-quality graphene and silicene two dimensional layers and understanding the properties of interface between graphene or silicene two dimensional layers and substrates play an indispensable role for realizing their potential applications in nanoelectronics. This thesis attempts to paint a clear picture about the growth mechanism of graphene from Polycyclic aromatic hydrocarbons (PAHs) on Cu(111) surface and interfacial electronic properties of graphene and silicene to promote application of Two Dimensional Group IV Semiconductor and shed light on rational design of functional devices. / Firstly, in order to obtain insights into the reaction mechanism, the bottom-up growth of graphene from PAHs on Cu(111) surface has been systematically analyzed by means of large-scale ab initio simulation in a density functional theory (DFT) framework. Theoretical calculation shows that the underlying growth mechanism, which mainly involves surface-mediated nucleation process of dehydrogenated PAHs rather than segregation or precipitation process of small carbon clusters decomposed from the precursors. The quality of the synthesized graphene sheets and minimum growth temperature strongly depends on the structures of PAHs as well as the molecular activities. Increasing the growth temperature will augment the activity of carbon clusters, so as to increase the probability in formation of prefect graphene sheets. Coronene, having 6-fold rotational symmetry and the same lattice as graphene, has the highest probability in forming high quality graphene, especially at relatively low growth temperature. / Secondly, the electronic properties of graphene supported by (0001) SiO₂ surface are theoretically studied using the density functional theory. It is found that the electronic attributes of graphene on (0001) SiO₂ strongly depend on the underlying SiO₂ surface properties and the percentage of hydrogen-passivation. By applying methyl to passivate oxygen-terminated (0001) SiO₂ surface one can further reduce the interaction between the graphene sheet and oxygen-terminated surface. This can improve the charge carrier mobility of graphene supported by SiO₂ substrate and reduce the influence by residual interfacial molecules. In addition, the external electric field modulates the charge transfer between graphene and the SiO₂ surface, when graphene layers are physisorbed on the oxide surface. This phenomenon will enhance the built-in electric field of bilayer graphene so as to effectively modify its band structure. Our results shed light on a better atomistic understanding of the recent experiments on graphene supported by SiO₂. / Based on the above two conclusions, the graphene/substrate interface properties and engineering of bottom-gated, large-scale triphenylene-derived graphene transistors by applying octadecyltrimethoxysilane (OTMS) self-assembled monolayers (SAM) onto the gate dielectric surface are studied. To meet the challenge that the isolated carbon monomers are likely to form defective carbon clusters with pentagons, at the initial stage of CVD graphene growth, triphenylene (C₁₈H₁₂) (pentagon-free with only C and H) was used as the solid precursor for high-quality and large-scale graphene synthesis. Transport measurements performed on back-gated graphene field-effect transistors (GFETs) with large channel lengths (~25 μm) show a carrier mobility up to ~5090 cm²V⁻¹s⁻¹ on SiO₂/Si substrate at room temperature under vacuum. Furthermore we show that in virtue of the ultrasmooth SAM surface and reduced interfacial impurity scattering as well as attenuated surface polar phonon scattering, the GFET carrier mobility on octadecyltrimethoxysilane (OTMS) passiviated SiO₂ surface is consistently improved up to ~9080 cm²V⁻¹s⁻¹, whose graphene active layer has been grown with triphenylene precursor. This makes it promising for practical applications. In addition, in comparison with the devices without interface engineering, triphenylene-derived GFETs with OTMS-SAM modified SiO₂/Si substrate exhibit the marked carrier-density-dependent field-effect mobility. Quantitative analyses reveal that at ambient temperature, the predominant scattering sources affect the carrier mean free path for graphene devices on bare SiO₂ substrates and for those on OTMS passivated SiO₂ substrates are charged impurity induced long-range scattering (~5.34×10¹¹ cm⁻² in carrier density) and resonant scattering (short-range scattering ~9.77×10¹° cm⁻² carrier in density), respectively. Our findings elucidate the underlying dominate factors for achieving the significantly improved device performance of GFETs at room temperature. / Finally, by exploiting first-principles calculations, we show that the band gap and electron effective mass (EEM) of various confined graphene and silicene (D-X/G/H-D, Si-X/S/H-Si and D-X/S/H-D) can be effectively modulated by tuning the pressure (interlayer spacing) and stacking arrangement. The electron effective mass (EEM) is proportional to the band gap. The band gap of confined silicene is more sensitive to pressure than that of confined graphene. Moreover, heterogeneous interface would be beneficial to effectively control the band gap and carrier effective masses of confined graphene and silicene. Using the confined technique and pressure, the integrity of the honeycomb structure of graphene and silicene will be preserved, so the small effective masses and high mobility of graphene and silicene will remain during compression. The tunable band gap and high carrier mobility of the sandwich structures are promising for building high-performance nanodevices. / The aforementioned four sub-topics form the mechanistic understanding of graphene growth by PAHs and interfacial electronic properties of graphene and silicene down to the molecular level. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Chen, Kun. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract --- p.II / 博士學位論文摘要： --- p.VI / Acknowledgements --- p.X / Chapter Chapter 1 --- Introduction to Growth Methods and Electronic Properties of Graphene and Silicene --- p.1 / Chapter 1.1 --- Electronic Properties of Graphene --- p.2 / Chapter 1.1.1 --- The Direct Lattice and the Reciprocal Lattice --- p.2 / Chapter 1.1.2 --- Electronic Band Structure --- p.6 / Chapter 1.1.3 --- Tight-Binding Energy Dispersion --- p.7 / Chapter 1.1.4 --- Massless Dirac Fermions --- p.15 / Chapter 1.1.5 --- Carrier Density and Effective Mass --- p.21 / Chapter 1.1.6 --- The Tight-Binding Model of Bilayer Graphene --- p.24 / Chapter 1.1.7 --- The Two-Component Hamiltonian of Bilayer Graphene --- p.29 / Chapter 1.1.8 --- Trigonal Warping in Graphene --- p.32 / Chapter 1.1.9 --- Tunable Band Gap in Bilayer Graphene --- p.36 / Chapter 1.2 --- Synthesis of Graphene --- p.38 / Chapter 1.2.1 --- Exfoliation and Cleavage --- p.39 / Chapter 1.2.2 --- Thermal Decomposition of SiC --- p.40 / Chapter 1.2.3 --- Chemical Vapor Deposition of Graphene --- p.42 / Chapter 1.3 --- Electronic Properties at Graphene/Substrate Interface --- p.55 / Chapter 1.3.1 --- Graphene on SiO₂/Si Substrates --- p.56 / Chapter 1.3.2 --- Graphene on Hexagonal Boron Nitride (h-BN) --- p.60 / Chapter 1.3.3 --- Graphene on Organic Self-Assembled Monolayer (SAM) Passivation of Bared SiO₂/Si --- p.61 / Chapter 1.4 --- Synthesis and Electronic Properties of Silicene --- p.63 / Chapter 1.4.1 --- Synthesis of Silicene --- p.64 / Chapter 1.4.2 --- Electronic Properties of Silicene --- p.65 / Chapter References --- p.67 / Chapter Chapter 2 --- Introduction to Density Functional Theory --- p.75 / Chapter 2.1 --- Many-Particle Hamiltonian --- p.75 / Chapter 2.2 --- Born-Oppenheimer Approximation --- p.76 / Chapter 2.3 --- Hartree-Fock Method --- p.77 / Chapter 2.4 --- Density Functional Theory (DFT) --- p.77 / Chapter 2.4.1 --- Hohenberg-Kohn Theorems --- p.77 / Chapter 2.4.2 --- Kohn-Sham Method --- p.79 / Chapter 2.4.3 --- Kohn-Sham Equation --- p.80 / Chapter 2.4.4 --- Solution of Kohn-Sham Equation --- p.80 / Chapter 2.5 --- Electron Density Approximation --- p.80 / Chapter 2.5.1 --- Local Density Approximation (LDA) --- p.80 / Chapter 2.5.2 --- Generalized Gradient Approximation (GGA) --- p.82 / Chapter 2.5.3 --- Hybrid Functionals --- p.82 / Chapter 2.6 --- Plane Waves Expansion --- p.83 / Chapter 2.7 --- Pseudopotentials --- p.84 / Chapter 2.7.1 --- Ultrasoft Pseudopotentials (USPP) --- p.86 / Chapter 2.7.2 --- Projector Augmented Wave Potentials (PAW) --- p.87 / Chapter 2.8 --- DFT+U --- p.88 / Chapter References --- p.89 / Chapter Chapter 3 --- ab initio Study of Growth Mechanism of Graphene from Polycyclic Aromatic Hydrocarbons --- p.91 / Chapter 3.1 --- Introduction --- p.91 / Chapter 3.2 --- Experimental Results --- p.93 / Chapter 3.3 --- Calculation Method --- p.94 / Chapter 3.4 --- Calculation Results and Discussion --- p.96 / Chapter 3.5 --- Conclusion --- p.109 / Chapter References --- p.109 / Chapter Chapter 4 --- Electronic Properties of Graphene Altered by Substrate Surface Chemistry and Externally Applied Electric Field --- p.113 / Chapter 4.1 --- Introduction --- p.113 / Chapter 4.2 --- Calculation Method --- p.115 / Chapter 4.3 --- Results and Discussion --- p.116 / Chapter 4.4 --- Conclusions --- p.133 / Chapter References --- p.134 / Chapter Chapter 5 --- High Performance Devices Based on Large-Scale Triphenylene Derived Graphene and Interface Engineering --- p.138 / Chapter 5.1 --- Introduction --- p.138 / Chapter 5.2 --- Experimental Section --- p.140 / Chapter 5.3 --- Results and Discussion --- p.144 / Chapter 5.4 --- Conclusion --- p.163 / Chapter References --- p.164 / Chapter Chapter 6 --- Controllable Modulation of Electronic Properties of Graphene and Silicene by Interface Engineering and Pressure --- p.169 / Chapter 6.1 --- Introduction --- p.169 / Chapter 6.2 --- Modeling and Methods --- p.171 / Chapter 6.3 --- Results and Discussion --- p.174 / Chapter 6.4 --- Conclutions --- p.200 / Chapter References --- p.201 / Chapter Chapter 7 --- Conclusions and Future Plans --- p.204 / Chapter 7.1 --- Conclusions --- p.204 / Chapter 7.2 --- Future Plans --- p.206 / List of Publications during Ph.D. Study --- p.207

Graduation date: 1994