The failure of integrated circuit due to Silicon fracture is one of the problems associated with the production of a semiconductor device. The thermal stresses, which result in die cracking, are for the most part induced during the cooling process after attaching the die with Gold-Silicon solder. Major factors for stress generation in material systems are commonly large temperature gradients and substantial difference in coefficients of thermal expansion.

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Graduation date: 1995

We present a theoretical study of quasi-adiabatic clocking and thermal effect in Quantum-dot Cellular Automata (QCA). Quasi-adiabatic clocking is the modulation of an inter-dot potential barrier in order to keep the QCA cells near the ground state throughout the switching process. A time-dependent electric field is calculated for arrays of charged rods. The electron tunneling between dots is controlled by raising and lowering a potential barrier in the cell.A quantum statistical model has been introduced to obtain the thermal average of polarization of a QCA cell. We have studied the thermal effect on QCA devices. The theoretical analysis has been approximated for a two-state model where the cells are in one of two possible eigenstates of the cell Hamiltonian. In general, the average polarization of each cell decreases with temperature and the distance from the driver cells. The results demonstrate the critical nature of temperature dependence for the operation of QCA. / Department of Physics and Astronomy

Areas which require high-temperature MOS circuits are instrumentations for geothermal and petroleum well-logging, space exploration, aero-propulsion systems, and other hostile environments. MOS digital circuits at high temperature are examined as well as the maximum operating temperature of MOS devices. Factors affecting high-temperature operation of these devices, including threshold voltage sensitivity, mobility degradation, leakage current characterization and interactions, zero-TC current in analog applications and reliability considerations, are discussed. Methods to reduce threshold voltage sensitivities, process modifications to reduce leakage current density at high temperature, circuit techniques to eliminate the leakage current effects, diode compensation, CMOS thermal latch-up and MOS scaling rules at high temperature are investigated. Experimental results of epitaxial diodes to verify the leakage current reduction effect are discussed.

Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Electrical and Computer Engineering.

The low thermal conductivity of gallium arsenide compared to silicon results in self-heating effects in GaAs MESFETs that limit the electrical performance of such devices for high power applications. To date, analytical thermal models of self heating in GaAs MESFETs are based on the assumption of a uniformly heated channel. This thesis presents a two dimensional analysis of the electrothermal effect of this device based on the two dimensional power density distribution in the channel under various bias conditions. The numerical simulation is performed using the finite difference technique. The results of the simulation of an isothermal MESFET without heat effects is compared with various one dimensional analytical models in the literature. Electro thermal effects into the two-dimensional isothermal MESFET model allowed close examination of the temperature profile within the MESFET. The large gradient in power distribution results in a localized heat source within the channel which increases the overall channel temperature, which shows that the assumption of a uniformly heated channel is erroneous, and may lead to an underestimation of the maximum channel temperature. / Graduation date: 1992

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.