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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A CMOS LNA for 3.1-10.6GHz Ultra-Wideband

Lin, Shin-Yang 25 January 2011 (has links)
The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.
2

Design of an UWB CMOS Low Noise Amplifier with Series-peaking

Miao, Jen-hao 25 January 2010 (has links)
The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration and resistive-feedback, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. The total power dissipation of the low noise amplifier is about 24.3mW at power supply 1.5 volt and the chip size is 1.283*1.008mm2. The simulated result shows that S11 is under -8dB, S22 is under -10dB, the forward gain S21 is 12.6dB~15.3dB at 3.1-10.6GHz, the reverse isolation S12 is under -30dB, and the noise figure is 3.24dB~4.84dB.

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