The main contents of this thesis are improving a UWB LNA, and analyze the input-matching, the noise, and the gain. First we increase the width of the input transistor, and remove source-degeneration inductor. Those ways can increase the gain and reduce the noise of the circuit. In the input matching, we use a shunt capacitor, a series inductor, and the impedance of the transistor itself to achieve high frequency matching. The lower frequency matching is achieved by negative feedback resistor. The UWB LNA dissipates 10.14 mW power and achieves input return loss (S11) below -11.5 dB, output return loss (S22) below -11.9 dB, forward gain (S21) of 14.4¡Ó0.4 dB, reverse isolation (S12) below -26.7 dB, and noise figure (NF) of 2.6~3.5 dB over the 3.1~10.6 GHz band of interest. 1-dB compression point (P1dB) of -16.8 dBm and input third-order inter-modulation point (IIP3) of -8.1 dBm are achieved at 6.85 GHz.

The main contents of this thesis are improving a UWB LNA, and analyze the input-matching, the noise, and the gain. First we use the feedback of the input transistor , and it different from the traditional source-degeneration inductor.The design can increase the gain and reduce the noise of the circuit.The second stage CS architecture designed to improve the overall gain of the circuit. Output level to use the source follower with the device even when the output matching . In the input matching,we use a shunt inductor and the impedance of the transistor itself to achieve high frequency matching. The UWB LNA dissipates 16.8 mW power and achieves input return loss (S11) -9.3 to -10 dB, output return loss (S22) -16.83 to -13 dB, forward gain (S21) 13.8 to 11.6 dB, reverse isolation (S12) below -30 dB, and noise figure (NF) of 2.38~3.31 dB over the 6~10 GHz band of interest. 1-dB compression point (P1dB) of -12.5 dBm and input third-order inter-modulation point (IIP3) of -2.5 dBm are achieved at 6 GHz.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration and resistive-feedback, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. The total power dissipation of the low noise amplifier is about 24.3mW at power supply 1.5 volt and the chip size is 1.283*1.008mm2. The simulated result shows that S11 is under -8dB, S22 is under -10dB, the forward gain S21 is 12.6dB~15.3dB at 3.1-10.6GHz, the reverse isolation S12 is under -30dB, and the noise figure is 3.24dB~4.84dB.