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The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach of design, analysis and simulation. The metallic SET transistors considered in this work are fabricated within the chip interconnect layers using CMOS back-end-of-line (BEOL)-compatible processing. The CMOS process integration can be divided into front-end-of-line (FEOL) and BEOL processes. The FEOL includes processes required to form isolated CMOS transistors whereas BEOL is the second portion of the IC fabrication where the devices get interconnected through the wiring using multiple layers of dielectrics and metals. Therefore, metallic SET circuits can be easily stacked above the CMOS platform presenting a low cost, low thermal budget, improving the overall yield at high-volume production of highly integrated systems. This considerably decreases the interconnect parasitics and increases the density of functions while maintaining the overall acceptable performance. Many problems such as low current drivability, delay and small voltage gain that hinder SET technology for its implementation in integrated circuits can be alleviated by intelligent circuit design. Although a complete replacement of CMOS by SETs is unlikely in the near future, an augmentation of CMOS with SETs is desirable if interfacing from and to CMOS works well. Interfacing from CMOS to SET circuitry is simple as the current and voltage levels are small and in accessible range. But interfacing CMOS from SET circuits is delicate due to SET logic's low current driving capability for CMOS and its interconnect. There is no concrete research on the interface issue wherein a SET-only circuitry drives a CMOS and its interconnects. For such hybridization to become possible, it is necessary to demonstrate the SET logic driving capability for CMOS with sufficient current drive and output voltage. The core SET logic can be designed to operate at low voltage, but at the interface the output of the SET logic must be in a voltage range that can be fed to a CMOS input for proper logic functionality. It is hence necessary to develop and adopt a systematic design methodology for such hybrid circuits at a specific technology node for room temperature operation. In this thesis we will look at a generalized design methodology that can be applied to (a) develop a fabrication model with parasitic effect of a hybrid SET-CMOS and SET-only circuits, (b) design and analyze the SET based fundamental building block in hybrid SET-CMOS or SET-only circuit and (c) simulate such a circuitry to assess its merits. More specifically, we will address the interfacing issue of such hybrid circuits in which we exploit the maximum capability of a SET logic in terms of driving capability, voltage response and power for a room temperature operation. The result of this research motivates the application of SET logic in 2 stages realizing some properties beyond those of CMOS devices. The first stage is the heterogeneous integration at chip level around a CMOS core. In such a circuitry, the SET introduces new functionalities such as reconfigurable logic, random number-based circuits, and multiband filtering circuits that can be combined with CMOS based general purpose processors or I/O signal restoration. The second stage of application is to use a new information processing technology focussed on a "new switch" exploiting a new state variable to provide functional scaling substantially beyond that attainable solely with ultimately scaled CMOS.

In leading up to the proof, methods for constructing fields and finitely additive set functions are introduced with an application involving the Tagaki function given as an example. Also, non-absolutely continuous set functions are constructed using Banach limits and maximal filters.

The aim of this work is the study of infinite conformal iterated function systems. More specifically, we investigate some properties of a limit set J associated to such system, its Hausdorff and packing measure and Hausdorff dimension. We provide necessary and sufficient conditions for such systems to be bi-Lipschitz equivalent. We use the concept of scaling functions to obtain some result about 1-dimensional systems. We discuss particular examples of infinite iterated function systems derived from complex continued fraction expansions with restricted entries. Each system is obtained from an infinite number of contractions. We show that under certain conditions the limit sets of such systems possess zero Hausdorff measure and positive finite packing measure. We include an algorithm for an approximation of the Hausdorff dimension of limit sets. One numerical result is presented. In this thesis we also explore the concept of positively recurrent function. We use iterated function systems to construct a natural, wide class of such functions that have strong ergodic properties.

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In this thesis, we present a number of results in set theory, particularly in the areas of forcing, large cardinals, and combinatorial set theory. Chapter 2 concerns covering matrices, combinatorial structures introduced by Viale in his proof that the Singular Cardinals Hypothesis follows from the Proper Forcing Axiom. In the course of this proof and subsequent work with Sharon, Viale isolated two reflection principles, CP and S, which can hold of covering matrices. We investigate covering matrices for which CP and S fail and prove some results about the connections between such covering matrices and various square principles. In Chapter 3, motivated by the results of Chapter 2, we introduce a number of square principles intermediate between the classical and (+). We provide a detailed picture of the implications and independence results which exist between these principles when is regular. In Chapter 4, we address three questions raised by Cummings and Foreman regarding a model of Gitik and Sharon. We first analyze the PCF-theoretic structure of the Gitik-Sharon model, determining the extent of good and bad scales. We then classify the bad points of the bad scales existing in both the Gitik-Sharon model and various other models containing bad scales. Finally, we investigate the ideal of subsets of singular cardinals of countable cofinality carrying good scales. In Chapter 5, we prove that, assuming large cardinals, it is consistent that there are many singular cardinals such that every stationary subset of + reflects but there are stationary subsets of + that do not reflect at ordinals of arbitrarily high cofinality. This answers a question raised by Todd Eisworth and is joint work with James Cummings. In Chapter 6, we extend a result of Gitik, Kanovei, and Koepke regarding intermediate models of Prikry-generic forcing extensions to Radin generic forcing extensions. Specifically, we characterize intermediate models of forcing extensions by Radin forcing at a large cardinal using measure sequences of length less than. In the final brief chapter, we prove some results about iterations of w1-Cohen forcing with w1-support, answering a question of Justin Moore.

Thesis (Ph.D.)--University of Delaware, 2008. / Principal faculty advisor: Robert Coulter, Dept. of Mathematical Sciences. Includes bibliographical references.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1970. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Pas de résumé / The level set method was introduced by Osher & Sethian (1988) as a general technique to capture moving interfaces. It has been used to study crystal growth, to simulate water and fire for computer graphics applications, to study two-phase flows and in many other fields. The wellknown problem of the level set method is the following: if the flow velocity is not constant, the level set scalar may become strongly distorted. Thus, the numerical integration may suffer from loss of accuracy. In level set methods, this problem is remedied by the reinitialization procedure, i.e. by reconstruction of the level set function in a way to satisfy the eikonal equation. We propose an alternative approach. We modify directly the level set equation by embedding a source term. The exact expression of this term is such that the eikonal equation is automatically satisfied. Furthermore on the interface, this term is equal to zero. In the meantime, the advantage of our approach is this: the exact expression of the source term allows for the possibility of derivation of its local approximate forms, of first-and-higher order accuracy. Compared to the extension velocity method, this may open the simplifications in realization of level set methods. Compared to the standard approach with the reinitialization procedure, this may give the economies in the number of level set re-initializations, and also, due to reduced number of reinitializations, one may expect an improvement in resolution of zero-set level. Hence, the objective of the present dissertation is to describe and to assess this approach in different test cases.