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1	Settling Time Reducibility Orderings Loo, Clinton 26 April 2010 (has links) It is known that orderings can be formed with settling time domination and strong settling time domination as relations on c.e. sets. However, it has been shown that no such ordering can be formed when considering computation time domination as a relation on $n$-c.e. sets where $n \geq 3$. This will be extended to the case of $2$-c.e. sets, showing that no ordering can be derived from computation time domination on $n$-c.e. sets when $n\geq 2$. Additionally, we will observe properties of the orderings given by settling time domination and strong settling time domination on c.e. sets, respectively denoted as $\mathcal{E}_{st}$ and $\mathcal{E}_{sst}$. More specifically, it is already known that any countable partial ordering can be embedded into $\mathcal{E}_{st}$ and any linear ordering with no infinite ascending chains can be embedded into $\mathcal{E}_{sst}$. Continuing along this line, we will show that any finite partial ordering can be embedded into $\mathcal{E}_{sst}$. Pure Mathematics
2	Settling Time Reducibility Orderings Loo, Clinton 26 April 2010 (has links) It is known that orderings can be formed with settling time domination and strong settling time domination as relations on c.e. sets. However, it has been shown that no such ordering can be formed when considering computation time domination as a relation on $n$-c.e. sets where $n \geq 3$. This will be extended to the case of $2$-c.e. sets, showing that no ordering can be derived from computation time domination on $n$-c.e. sets when $n\geq 2$. Additionally, we will observe properties of the orderings given by settling time domination and strong settling time domination on c.e. sets, respectively denoted as $\mathcal{E}_{st}$ and $\mathcal{E}_{sst}$. More specifically, it is already known that any countable partial ordering can be embedded into $\mathcal{E}_{st}$ and any linear ordering with no infinite ascending chains can be embedded into $\mathcal{E}_{sst}$. Continuing along this line, we will show that any finite partial ordering can be embedded into $\mathcal{E}_{sst}$. Pure Mathematics
3	Study and Realisation of Nyquist Rate Filters in Voltage Inverter Switch Technique Bharadhwaj, Harsha January 2006 (has links) <p>Low-sensitivity switched capacitor filters imitating 'R','L' and 'C' can be built by means of capacitances, ordinary switches and voltage inverter switches (VIS). These structures carry the inherent bilinear transformation of their doubly resistively terminated ladder reference filters. This one to one correspondence between the 's-domain' and the 'z-domain' results in the Nyquist criterion being the only limitation on the sampling frequency. This eliminates the necessity for oversampling and VIS filters can be designed for high operating rates.</p><p>Filters based on VIS principle were analysed in previous literatures in the 'phi-domain'. In this thesis work, a successful attempt has been made to formulate an analysis procedure for discrete-time filters based on VIS principle in the 'z-domain'. Significant details have been brought out in comparison with the respective reference filter. A fifth-order lowpass filter has been designed and implemented to exhibit the closeness to the bilinearly transformed continuous-time reference filter. Settling time analysis has been done to justify the need for filters using VIS principle as compared to the filters employing integrator based switched capacitor filter. It is shown that VIS filter can be made to settle within half the period required for a conventional integrator based switched capacitor filter.</p> Voltage Inverter Switch VIS Settling time Discrete time filters Bilinear transformation Electrical engineering Elektroteknik
4	Study and Realisation of Nyquist Rate Filters in Voltage Inverter Switch Technique Bharadhwaj, Harsha January 2006 (has links) Low-sensitivity switched capacitor filters imitating 'R','L' and 'C' can be built by means of capacitances, ordinary switches and voltage inverter switches (VIS). These structures carry the inherent bilinear transformation of their doubly resistively terminated ladder reference filters. This one to one correspondence between the 's-domain' and the 'z-domain' results in the Nyquist criterion being the only limitation on the sampling frequency. This eliminates the necessity for oversampling and VIS filters can be designed for high operating rates. Filters based on VIS principle were analysed in previous literatures in the 'phi-domain'. In this thesis work, a successful attempt has been made to formulate an analysis procedure for discrete-time filters based on VIS principle in the 'z-domain'. Significant details have been brought out in comparison with the respective reference filter. A fifth-order lowpass filter has been designed and implemented to exhibit the closeness to the bilinearly transformed continuous-time reference filter. Settling time analysis has been done to justify the need for filters using VIS principle as compared to the filters employing integrator based switched capacitor filter. It is shown that VIS filter can be made to settle within half the period required for a conventional integrator based switched capacitor filter. Voltage Inverter Switch VIS Settling time Discrete time filters Bilinear transformation Electrical engineering Elektroteknik
5	Settling Time Measurement Techniques Achieving High Precision at High Speeds Kayabasi, Cezmi 05 May 2005 (has links) Settling time is very important for data acquisition systems because it is the primary factor that defines the data rate for a given error level. Therefore settling time measurement is a crucial test. The goal of the project was to design, test and compare different measurement techniques. Three methods were tested to the accuracies of 0.1% and 0.01%. Also simulations were conducted to explain the parameters that affect the settling behavior. Additionally bench measurements were correlated to simulation results. This report is intended as a guide for settling time measurements. high speed high precision settling method measurement settling time guide theory definition comparison Automatic data collection systems Amplifiers Operational
6	Slag Cleaning of a Reduced Iron Silicate Slag by Settling : Influence of Process Parameters and Slag Modification on Copper Content Isaksson, Jenny January 2021 (has links) During the pyrometallurgical extraction of copper, a significant part of the copper is lost with discard slag, which decreases profits, overall copper recovery, and efficiency of raw material usage. Smelting furnace slag usually has a copper content that is close to or higher than that of copper ores. The investigation of copper losses to slag is thus a task of practical significance, as the ore grades are depleting. Slag cleaning, e.g., a settling furnace, can reduce copper losses to slag as the mechanically suspended copper-containing droplets separate from slag under the action of gravity and can hence be recovered. An industrial trial was conducted in an electric settling furnace with slag originating from an electric smelting furnace and processed in a zinc fuming furnace. The trial was conducted to increase the understanding of copper losses to slag and how the process parameters temperature and settling time influence the slag copper content. The obtained slag samples were also evaluated to gain better insights as to the settling mechanism and, if any, factors that hinder the copper phases from settling. Slag modification with CaO was also evaluated to investigate how the modification influences the settling of copper phases and, thus, the final slag copper content. Samples collected during the industrial trial were the basis for the evaluation in the current work. The samples came from batches with varying temperatures, settling times, and CaO content collected at four different sample positions. Instrumental techniques, including XRF, FAAS, ICP-SFMS, and SEM-EDS, were used to analyze the chemical compositions of the samples and the appearance of copper and associated phases. The results indicated that the copper content of outgoing slag increased with increasing temperature in the evaluated interval. The copper content was also concluded to be more strongly affected by the temperature compared to the settling time. Regulating the temperature to the lower temperature interval in the settling furnace could thus decrease the final slag copper content. During the slag characterization, it was found that suspended copper-containing phases were hindered from settling, due to the attachment to solid phases and gas bubbles in the slag. By controlling and minimizing the presence of the bottom buildup and thus solid phases in the slag, the copper content can be decreased. The results indicated that the CaO slag modification decreased the final slag copper content, and can thus be used as a modifier for increased settling. Copper losses matte speiss fayalite slag temperature settling time solid phases industrial trial CaO modification Metallurgy and Metallic Materials Metallurgi och metalliska material
7	Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS / Energi-effektiva metoder för att minska insvängningstiden för en folded-cascodeförstärkare i 1.8V, 0.18um CMOS Johansson, Jimmy January 2017 (has links) Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions. Folded-Cascode Settling Time Settling Time Reduction Slew Rate Slew Rate Enhancement Operational Amplifier Recycling Folded-Cascode 180 nm CMOS Test Buffer Power-Efficient Single-Stage Amplifier Linear Settling Period Slewing Period Annan elektroteknik och elektronik
8	Settling-Time Improvements in Positioning Machines Subject to Nonlinear Friction Using Adaptive Impulse Control Hakala, Tim 31 January 2006 (has links) (PDF) A new method of adaptive impulse control is developed to precisely and quickly control the position of machine components subject to friction. Friction dominates the forces affecting fine positioning dynamics. Friction can depend on payload, velocity, step size, path, initial position, temperature, and other variables. Control problems such as steady-state error and limit cycles often arise when applying conventional control techniques to the position control problem. Studies in the last few decades have shown that impulsive control can produce repeatable displacements as small as ten nanometers without limit cycles or steady-state error in machines subject to dry sliding friction. These displacements are achieved through the application of short duration, high intensity pulses. The relationship between pulse duration and displacement is seldom a simple function. The most dependable practical methods for control are self-tuning; they learn from online experience by adapting an internal control parameter until precise position control is achieved. To date, the best known adaptive pulse control methods adapt a single control parameter. While effective, the single parameter methods suffer from sub-optimal settling times and poor parameter convergence. To improve performance while maintaining the capacity for ultimate precision, a new control method referred to as Adaptive Impulse Control (AIC) has been developed. To better fit the nonlinear relationship between pulses and displacements, AIC adaptively tunes a set of parameters. Each parameter affects a different range of displacements. Online updates depend on the residual control error following each pulse, an estimate of pulse sensitivity, and a learning gain. After an update is calculated, it is distributed among the parameters that were used to calculate the most recent pulse. As the stored relationship converges to the actual relationship of the machine, pulses become more accurate and fewer pulses are needed to reach each desired destination. When fewer pulses are needed, settling time improves and efficiency increases. AIC is experimentally compared to conventional PID control and other adaptive pulse control methods on a rotary system with a position measurement resolution of 16000 encoder counts per revolution of the load wheel. The friction in the test system is nonlinear and irregular with a position dependent break-away torque that varies by a factor of more than 1.8 to 1. AIC is shown to improve settling times by as much as a factor of two when compared to other adaptive pulse control methods while maintaining precise control tolerances. control position adaptive impulsive settling-time nonlinear friction pulses displacements precise tolerances log-spaced update distributed learning Coulomb Stribeck Tomizuka Yang AIC PID MRAC STR RTAI Linux FreeBSD kernel modules microcontroller convergence practical self-tuning methods techniques limit-cycles steady-state error zero stable stability bound envelope partitioned scheme lookup-table multi-point adaptation repeatable mean servo motor exponential square-law rise-time real-time log-log interpolation pro-forma curve-fit sensitivity compliance variable static dynamic response torque acceleration velocity optical encoder parameters evolution fixed-law enhanced split weighting initialization trajectory layered processes Mechanical Engineering

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