The demand for low power wireless transceiver implementations has been fueled by multiple applications in the recent decades, including cellular systems, wireless local area networks, personal area networks, biotelemetry and sensor networks. Dynamic range, which is set by linearity and sensitivity performance, is a critical design metric in many of these systems. Both linearity and sensitivity requirements continue to become progressively challenging in many systems due to greater spectrum usage and the need for high data rates respectively. The objective of this research is to investigate power-efficient circuit techniques for reducing the power requirement in receiver front-ends without compromising the dynamic range performance. In the first part of the dissertation, a low power receiver down-converter topology for enhancing dynamic range performance is presented. Current mode down-converters with passive mixer cores have been shown to provide excellent dynamic range performance. However, in contrast to a current commutating Gilbert cell, these down-converters require separate bias current paths for the RF transconductor and the baseband transimpedance amplifier. The proposed topology reduces the power requirement of conventional current mode passive down-converter by sharing the bias current between the transconductance and transimpedance stages. This is achieved without compromising the available voltage headroom for either stage, which is a limitation of bias-sharing based on the use of stacked stages. The dynamic range of the basic bias-current-shared topology is further enhanced through suppression of low frequency noise and IM3 products. Two variants of the down-converter, employing a broadband common-gate and a narrowband common-source input stage, are implemented in a 0.18-μm CMOS technology. The dynamic range performance of the architecture is analyzed. Finally, a prototype of a full direct-conversion receiver implementation with quadrature outputs and integrated LO synthesis is demonstrated. A power-efficient oscillator design for phase noise minimization is presented in the second part of this dissertation. This design is targeted towards multi-radio platforms where several communication links operate simultaneously over multiple frequency bands. Blockers from concurrently operating radios present a major design challenge. The blockers not only make the frontend linearity requirement more stringent but also degrade receiver sensitivity through reciprocal mixing with the phase noise sidebands of LO. Phase noise minimization is thus critical for ensuring high sensitivity in frequency bands where large blockers are present and not sufficiently attenuated by pre-select filters. A capacitive power combining technique in oscillators is introduced to improve phase noise performance. By combining this approach with current reuse, the phase noise is reduced at lower power, compared to conventional LC oscillators. This leads to improved power efficiency. Moreover, the technique mitigates modeling uncertainty arising from phase noise reduction through simultaneous impedance and current scaling. The mode selection in this oscillator, which employs multiple coupled resonators, is analyzed and the impact of coupling on far-out phase noise performance is discussed. Multi-mode oscillation can potentially arise in other oscillator topologies too, e.g., in multiphase oscillators. Mode selection in a widely used transistor-coupled quadrature oscillator is analyzed in detail in the final part of the dissertation. The analysis shows how cross-compression among multiple competing modes can lead to suppression of non-dominant modes in the steady state. / text