Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: Please refer to full text for abstract.

The aim of this work is to propose the involvement of a monitoring receiver for air band and its practical realization. The receiver is controlled from a PC via USB, after which it is transmitted simultaneously digitized audio signal. The receiver can be controlled from a PC, or some basic function by buttons.

In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.

<p>In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. </p><p>Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. </p><p>The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. </p><p>The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.</p>

The demand for low power wireless transceiver implementations has been fueled by multiple applications in the recent decades, including cellular systems, wireless local area networks, personal area networks, biotelemetry and sensor networks. Dynamic range, which is set by linearity and sensitivity performance, is a critical design metric in many of these systems. Both linearity and sensitivity requirements continue to become progressively challenging in many systems due to greater spectrum usage and the need for high data rates respectively. The objective of this research is to investigate power-efficient circuit techniques for reducing the power requirement in receiver front-ends without compromising the dynamic range performance. In the first part of the dissertation, a low power receiver down-converter topology for enhancing dynamic range performance is presented. Current mode down-converters with passive mixer cores have been shown to provide excellent dynamic range performance. However, in contrast to a current commutating Gilbert cell, these down-converters require separate bias current paths for the RF transconductor and the baseband transimpedance amplifier. The proposed topology reduces the power requirement of conventional current mode passive down-converter by sharing the bias current between the transconductance and transimpedance stages. This is achieved without compromising the available voltage headroom for either stage, which is a limitation of bias-sharing based on the use of stacked stages. The dynamic range of the basic bias-current-shared topology is further enhanced through suppression of low frequency noise and IM3 products. Two variants of the down-converter, employing a broadband common-gate and a narrowband common-source input stage, are implemented in a 0.18-μm CMOS technology. The dynamic range performance of the architecture is analyzed. Finally, a prototype of a full direct-conversion receiver implementation with quadrature outputs and integrated LO synthesis is demonstrated. A power-efficient oscillator design for phase noise minimization is presented in the second part of this dissertation. This design is targeted towards multi-radio platforms where several communication links operate simultaneously over multiple frequency bands. Blockers from concurrently operating radios present a major design challenge. The blockers not only make the frontend linearity requirement more stringent but also degrade receiver sensitivity through reciprocal mixing with the phase noise sidebands of LO. Phase noise minimization is thus critical for ensuring high sensitivity in frequency bands where large blockers are present and not sufficiently attenuated by pre-select filters. A capacitive power combining technique in oscillators is introduced to improve phase noise performance. By combining this approach with current reuse, the phase noise is reduced at lower power, compared to conventional LC oscillators. This leads to improved power efficiency. Moreover, the technique mitigates modeling uncertainty arising from phase noise reduction through simultaneous impedance and current scaling. The mode selection in this oscillator, which employs multiple coupled resonators, is analyzed and the impact of coupling on far-out phase noise performance is discussed. Multi-mode oscillation can potentially arise in other oscillator topologies too, e.g., in multiphase oscillators. Mode selection in a widely used transistor-coupled quadrature oscillator is analyzed in detail in the final part of the dissertation. The analysis shows how cross-compression among multiple competing modes can lead to suppression of non-dominant modes in the steady state. / text

This dissertation investigates Ultra-Wideband (UWB) techniques for the next generation Radio Frequency Identification (RFID) towards the Internet-of-Things (IoT). In particular, an ultra-high frequency (UHF) wireless-powered UWB radio (UHF/UWB hybrid) with asymmetric links is explored from system architecture to circuit implementation. Context-aware, location-aware, and energy-aware computing for the IoT demands future micro-devices (e.g., RFID tags) with capabilities of sensing, processing, communication, and positioning, which can be integrated into everyday objects including paper documents, as well as food and pharmaceutical packages. To this end, reliable-operating and maintenance-free wireless networks with low-power and low-cost radio transceivers are essential. In this context, state-of-the-art passive RFID technologies provide limited data rate and positioning accuracy, whereas active radios suffer from high complexity and power-hungry transceivers. Impulse Radio UWB (IR-UWB) exhibits significant advantages that are expected to overcome these limitations. Wideband signals offer robust communications and high-precision positioning; duty-cycled operations allow link scalability; and baseband-like architecture facilitates extremely simple and low-power transmitters. However, the implementation of the IR-UWB receiver is still power-hungry and complex, and thus is unacceptable for self-powered or passive tags. To cope with μW level power budget in wireless-powered systems, this dissertation proposes an UHF/UWB hybrid radio architecture with asymmetric links. It combines the passive UHF RFID and the IR-UWB transmitter. In the downlink (reader-tag), the tag is powered and controlled by UHF signals as conventional passive UHF tags, whereas it uses an IR-UWB transmitter to send data for a short time at a high rate in the uplink (tag-reader). Such an innovative architecture takes advantage of UWB transmissions, while the tag avoids the complex UWB receiver by shifting the burden to the reader. A wireless-powered tag providing -18.5 dBm sensitivity UHF downlink and 10 Mb/s UWB uplink is implemented in 180 nm CMOS. At the reader side, a non-coherent energy detection IR-UWB receiver is designed to pair the tag. The receiver is featured by high energy-efficiency and flexibility that supports multi-mode operations. A novel synchronization scheme based on the energy offset is suggested. It allows fast synchronization between the reader and tags, without increasing the hardware complexity. Time-of-Arrival (TOA) estimation schemes are analyzed and developed for the reader, which enables tag localization. The receiver prototype is fabricated in 90 nm CMOS with 16.3 mW power consumption and -79 dBm sensitivity at 10 Mb/s data rate. The system concept is verified by the link measurement between the tag and the reader. Compared with current passive UHF RFID systems, the UHF/UWB hybrid solution provides an order of magnitude improvement in terms of the data rate and positioning accuracy brought by the IR-UWB uplink. / QC 20120110

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Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms which reduces power consumption of the receiver. The work in the thesis ranges from designing low power architecture of the receiver to experimentally verifying the functioning of the receiver. Concepts proposed in the thesis are: Low power adaptive architecture :-A baseband digital receiver design is proposed which changes its sampling frequency and bit-width based on interference detection and SNR estimation. The approach is based on Look-up-table (LUT) in the digital section of the receiver. Interference detector and SNR estimator has been proposed which suits this approach. Settings of different sections of digital receiver changes as sampling frequency and bit-width varies. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. It is shown that the power consumption by the digital baseband can be reduced by 85% (7 times) when there is no interference and SNR is high. Thus the proposed design meets our requirement of low power hardware. The design is coded in Verilog HDL and power and area estimation is done using Synopsys tools. Faster Simulation Methodologies :-Usually physical layer simulations are done on baseband equivalent model of the signal in the receiver chain. Simulating Physical layer algorithms on bandpass signals for BER evaluation is very time consuming. We need to do the bandpass simulations to capture the effect of quantization on bandpass signal in the receiver. We have developed a variance measuring simulation methodology for faster simulation which reduces simulation time by a factor of 10. Low power, Low area, Non-coherent, Non-data-aided joint tracking and acquisition algorithm :-Correlation is a very popular function used particularly in synchronization algorithms in the receivers. But correlation requires usage of multipliers. Multipliers are area and power consuming blocks. A very low power and low area joint tracking and acquisition algorithm is developed. The algorithm does not use any multiplier to synchronize. Even it avoids squaring and adding the signals to achieve non-coherency. Beside the algorithm is non-data-aided as well and does not require ROM to store the sequence. The Algorithm saves area/power of existing similar algorithms by 90%. Experimental setup for performance evaluation of the receiver :-The developed baseband architecture and algorithms are experimentally verified on a wireless test setup. Wireless test setup consists of FPGA board, VSGs, Oscilloscopes, Spectrum analyzer and a discrete component RF board. Packet error and packet loss measurement is done by varying channel conditions. Many practical and interesting issues dealing with wireless test setup infrastructure were encountered and resolved.