<p>An important component in many communication system is the digital to analog converter. The component is needed in order to convert real world analog quantities to digital quantities which are easier to process. As the market for hand held devices with wireless communication with the outer world has increased new approaches for sharing the frequency spectrum are needed. Therefore it would be interesting to look at the possibility to design an analog to digital converter that, in runtime, can change the frequency band converted, and hence the used standard. This thesis study one of the possibilities to design such an ADC, as a Σ∆ modulator, and more precise the structure called Cascade of resonators with distributed feedback and input (CRFB). The order of the modulator in this study is two.</p>

An important component in many communication system is the digital to analog converter. The component is needed in order to convert real world analog quantities to digital quantities which are easier to process. As the market for hand held devices with wireless communication with the outer world has increased new approaches for sharing the frequency spectrum are needed. Therefore it would be interesting to look at the possibility to design an analog to digital converter that, in runtime, can change the frequency band converted, and hence the used standard. This thesis study one of the possibilities to design such an ADC, as a Σ∆ modulator, and more precise the structure called Cascade of resonators with distributed feedback and input (CRFB). The order of the modulator in this study is two.

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.

Digital-to-Analog Converters (DAC) form the feedback element in sigma-delta modulators. Any non-linearity in the DAC directly degrades the linearity of the modulator at low and medium frequencies. Hence, there is a need for designing highly linear DACs when used in high performance sigma-delta modulators. In this work, the impact of current mismatch on the linearity performance (IM3 and SQNR) of a 4-bit current steering DAC is analyzed. A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits. A statistical element selection algorithm for linearizing DACs is proposed. Current sources within the required accuracy are selected from a large set of current sources available. As compared with existing calibration techniques, this technique achieves higher accuracy and is more robust to variations in process and temperature. In contrast to existing data weighted averaging techniques, this technique does not degrade SNR performance of the ADC. A 5th order, 500 MS/s, 20 MHz sigma-delta modulator macro-model was used to test the linearity of the DAC.

The work deals with the design of novel high order sigma-delta AD converter using switched-capacitors approach. Model of the ideal and real architecture of the third order sigma-delta modulator was designed in MATLAB SIMULINK. The comparison of the ideal and real model of sigma delta architecture is described in this thesis. On the basis of simulation results in MATLAB SIMULINK the stages of modulator on transistors level in CMOS technology were designed. Fully differential operational amplifier, switched capacitor integrator, summing amplifier, comparator, one bit digital to analog converter and nonoverlapping clock generator were designed. The circuit of third order sigma-delta modulator was simulated in CADENCE. Layout of operational amplifier and switched capacitor integrator was made. Through the use of MATLAB was designed decimation filter as well.

Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single-stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single-stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 μm mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.

The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis. / Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objektas – skaitmeninis Sigma-Delta garso galios SA keitiklis, jo sandaros tobulinamas bei eksperimentinis tyrimas. Disertacijos tikslas – pasiūlyti skaitmeninio Sigma-Delta garso galios SA keitiklio interpoliatoriaus struktūros tobulinimo bei keitiklio tyrimo metodus.

The increasing complexity of digital circuits forces the use of new technologies. New technologies have the advantage of reducing the circuit size and power consumption coupled with operation speed increasement. Most of signal processing operations migrated to the digital domain, thus, basic blocks like AD converters are needed in mixed-signal systems. Analog-todigital converters based on Sigma-Delta (ΣΔ) modulators stand out among the existing architectures because they cover a wide range of applications. The most common implementation of ΣΔ modulators in CMOS technology is based in switched-capacitor technique (SC), mainly due to its high performance and excellent linearity. However, the continuous reduction in the transistor physical dimensions requires a proportional reduction in the supply voltage levels, making difficult the design of analog circuits with conventional topologies. To overcome this problem, design techniques to analog circuits compatible with these new technologies were developed. This is the case of the technique known as switched-current (SI), which uses samples in the current domain to represent the signal information. This work presents the design of a switched-current Sigma-Delta modulator (SI-ΣΔM) using an architecture oriented to low-distortion applications. The architecture s main characteristic is the reduced sensitivity to integrator nonlinearities, leading to a significant increase in the signal-to-noise ratio (SNR) and dynamic range (DR) values, moreover, it permits the design of high-order modulators intrinsically stable. To demonstrate and verify the performance of the used strategy, based on a combination of circuit techniques and topology, a cascade 2-2 SI-ΣΔM was designed in a CMOS XFAB XC06 technology. Postlayout simulations show that the SNR reaches a maximum value of 80 dB and a dynamic range of approximately 87 dB, implying an effective resolution of 14.15 bits considering 20 kHz bandwidth. The prototype was sent to manufacturing and will be subject to laboratory tests when it returns. / A crescente complexidade dos circuitos digitais força o uso de novas tecnologias de fabricação. A mudança para tecnologias mais avançadas tem como vantagem a redução do tamanho do circuito e a diminuição do consumo de energia aliados ao aumento da velocidade de operação. Grande parte das operações envolvendo processamento de sinais migraram para o domínio digital, portanto, blocos básicos como conversores AD são necessários em sistemas de sinal misto. Conversores AD com base em moduladores do tipo Sigma-Delta (ΣΔ) destacam-se entre as arquiteturas existentes por cobrir uma ampla gama de aplicações. A implementação mais usual de moduladores ΣΔ em tecnologia CMOS baseia-se na técnica de capacitor-chaveado (SC), devido, principalmente, à sua elevada performance e excelente linearidade. Entretanto, a contínua redução das dimensões físicas dos transistores tem exigido uma redução proporcional dos níveis de tensão de alimentação, dificultando o projeto de circuitos analógicos com topologias convencionais. Para contornar este problema, técnicas de projeto de circuitos analógicos compatíveis com essas novas tecnologias foram desenvolvidas. Este é o caso da técnica conhecida como corrente chaveada (SI), que utiliza amostras sob a forma de corrente para a representação de sinais. Neste trabalho é apresentado o projeto de um modulador ΣΔ em modo corrente (SI-ΣΔM) empregando uma arquitetura orientada à aplicações de baixa distorção. Esta arquitetura tem como principal característica a reduzida sensibilidade às não-linearidades do integrador, conduzindo a uma significante melhora no valor da relação sinal-ruído (SNR) e faixa de excursão dinâmica (DR), além de permitir a concepção de moduladores ΣΔ de elevada ordem intrinsecamente estáveis. Para demonstrar e comprovar a performance da estratégia empregada, baseada na combinação de técnicas de circuito e de topologia, projetou-se um modulador SI-ΣΔ cascata 2-2 na tecnologia XFAB CMOS XC06. Simulações elétricas pós-layout revelam que o SNR atinge um valor máximo de 80 dB e uma faixa dinâmica de aproximadamente 87 dB, inferindo uma resolução efetiva de 14,15 bits considerando uma banda de interesse de 20 kHz. Por fim, o protótipo desenvolvido foi enviado para fabricação e será alvo de testes em laboratório quando retornar.

The scope of my master thesis is a designing computer sound interface including measurement of audio performance. This work is concerning both design analog front - ends and digital support circuits. The sigma delta Analog to Digital (ADC) and Digital to Analog (DAC) converters is included in this conception. Those converters has been made into two separate printed circuit boards. All signal paths in this circuitry are utilizing differential mode that are quoted as balanced among audio engineers. Modern circuit components are used in this design, such as fully differential operational amplifiers, electronically controlled gain preamplifiers, low drop linear stabilizers with low noise level, DC component suppression circuits and low jitter active components. Theoretical part of this thesis contains specification of choosed sound defitions, questioning audio program loudness leveling. Further criteria of suitable active and passive components are included. In this thesis the simulations of fundamental circuits block are meant likewise. Practical part involve complete layout of printed circuit boards of and prototyping. Designed prototype device has wide application usage. It is intended to use not only as industrial computers, but also as dedicated sound converters, measurement cards, mixing consoles, switching matrixes, active loudspeakers, embedded systems.

Le travail présenté dans ce mémoire concerne la réalisation d’un microsystème intégrant une centrale inertielle permettant la détection de mouvements. Le microsystème étudié est composé d’un accéléromètre capacitif associé à son électronique de traitement. L’accéléromètre capacitif a conduit à l’élaboration d’un outil logiciel afin de le pré-dimensionner. Ce pré-dimensionnement a été effectué en fonction des spécifications de l’application et de la technologie de fabrication. Cet outil intègre des modèles fluidiques et électrostatiques en vue de calculer des paramètres du modèle de l’accéléromètre pour une simulation système. L’électronique de traitement de l’accéléromètre capacitif a été conçue autour d’un convertisseur ”Sigma-Delta”. L’architecture ”Sigma-Delta” a nécessité des modifications pour pouvoir être adaptée au capteur. Nous avons alors développé, sous ”Matlab-Simulink”, une bibliothèque de composants permettant d’ajuster le fonctionnement du convertisseur. Une fois l’architecture optimisée et les caractéristiques des composants connues, la conception de l’architecture ”Sigma-Delta” est ainsi réalisable sous le logiciel CADENCE. / The aim of this thesis is the realisation of microsystem for movements detection. This microsystem is composed of capacitive accelerometers and of their electronics. The conception of capacitive accelerometers has induced developement of a software for the first dimensionnement of sensors. This software computes parameters of capacitive accelerometers thanks to electrostatic models, flow models, specifications of application and fabrication process. The electronics of capacitive accelerometer is a ”Sigma-Delta” convertor. The adaptation of convertor leads to developement of components libraries for ”Matlab-Simulink”. The simulation systems allows to fit parametres convertor for the application. After that,the conception of convertor under CADENCE software is then possible.