In this thesis, a switched-current sigma-delta modulator (SDM) with op-amp active integrator is proposed. The major study is focused on using the op-amp to reduce the input impedance for high speed and high solution and utilizes the dummy switch to decrease the clock feedthrough (CFT) error. We use a sample-and-hold circuit which consists of an op-amp active memory cell and a dummy switch circuit to implement the integrator. It is applied to the building blocks of SDM. The modulator is a second order sigma-delta modulator. A current comparator transforms the current signal into digital voltage signal. A single-bit digital-to-analog (D/A) feedback circuit is used to convert the one-bit digital output to the SI integrator .The modulator is designed in the current mode technique. The delta-sigma modulator simulates using the parameters of the TSMC 0.35£gm CMOS process. The simulation results show that the signal to noise plus distortion ratio (SNDR) is 72 dB, the sampling rate is 10.24MHz, the oversampling ratio is 128, the power consumption is 21mW, the dynamic range is about 70dB, and the power supply is 3.3V. Furthermore, the circuit is verified by cadence-hspice simulation.

Biosensors are extremely powerful analytical tools instrumental for detection and quantification of bio-molecules such as DNA, peptides and even metabolites. The recent decade has seen a surge in biosensing applications ranging from molecular diagnostics, environmental monitoring, basic life science research, forensics and biothreat monitoring. The existing biosensor systems of today, however, have several limitations. They are expensive, bulky in size, power hungry, hard to use and with access limited to core facilities. Among other disadvantages, these impediments discourage the availability of point-of-care testing and low cost in-vitro diagnostics (IVD) in locations such as developing and third world countries. The main bottleneck in the development of low-cost and compact biosensors is the effective and efficient integration of several complex components present inside a typical biosensor. These components are the sample preparation, biomolecular recognition, signal transduction and data analysis. With vii the recent advancements in very large scale integration (VLSI) and fabrication technologies, it is now possible to integrate several of these biosensing components into a small form factor. This thesis proposes leveraging the utilization of VLSI technology to develop a low-cost, miniature, portable, fast analysis, high throughput and low power consumption biosensor solution. Apart from the miniaturization bene- fits, employing VLSI technology facilitates low-cost, high yield and low process variation. We present complementary metal-oxide semiconductor (CMOS) integrated microsystem solutions for fluorescence, bioluminescence and electrochemical biosensing. Simulation models are provided for the microsystems and the specifications for the constituent components derived. A common problem in the transducer development of biosensors that we specifically focus on, is the presence of a large non-informative signal called the background signal. This background signal can be several orders of magnitudes higher than the signal of interest and it reduces the overall sensitivity of the biosensor. Existing transducer solutions rely on very high dynamic range, expensive and power hungry solutions to solve the problem of high background signal. To address the problem of overwhelming background signal, this thesis proposes an active background subtraction architecture merged with a Σ∆ modulator. The robust, versatile architecture can be conveniently employed for optical and electrochemical sensing. The proposed architecture attenuates the background signal very early in the signal chain, achieving high dyviii namic range while significantly relaxing the performance requirements of the subsequent circuit blocks in terms of power dissipation, area and bandwidth requirements. To validate the proposed solution, two CMOS IC prototypes were developed for optical and electrochemical sensing respectively. A 12 × 12 array of Σ∆ photodetector with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. The pixel performance has been validated with over 140dB dynamic range and the ability of subtract the background subtraction current validated from 10nA to 10fA. Real time pyrosequencing experiment has also been performed utilizing the photodetector array. A 12 × 12 array of Σ∆ electrochemical sensor with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. Capacitive charge redistribution circuit architecture for bipolar current measurements was employed. The circuit performance was validated over the wide input current range of 100nA to 1pA. / text

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Circuits for sampling and retention of analogue signals are commonly implemented with techniques such as switched capacitors (SC). SC circuits employing the storage of charge in a linear capacitor to represent a signal in the form of voltage. Operational Amplifiers (AmpOp's) are used to transfer the load of a capacitor to another, sampling and holding circuits for analogue signals in closed loop. Recently, another technique has been developed without the need of building linear capacitors, making possible projects compatible with VLSI CMOS processes. This technique, called Switched Current (SI), is characterized by processing the signals in the current form, and implemented through the memory retention of electric charge on the gate of a MOS transistor in saturation zone. The charge is hold in a gate-source voltage and hence the current in a transistor. In this model, the excursion of the signal is not directly dependent on the supply voltage, but dependent on the polarization and current signal. This makes the model attractive for low voltage. The technique does not require AmpOp's and capacitors. The speed of the circuit is not limited by AmpOp's and its gainbandwidth product, but by design and manufacturing process. This technique is not yet consolidated and its performance is still not competitive with SC circuits [1] However, SI circuits become interesting as they constitute an open field for future research and the opportunity to be fully implemented in processes manufacturing oriented to purely digital circuits. This work begins with a framework of the subject matter, placing the reader in the state of the art manufacturing technology and some implications that directly affect analog circuits. Are also presented in this section some implementations which serve to characterize what is being done recently in terms of Sigma Delta (ΣΔ) modulators. Abstract vi In Chapter 2, are made a review of sampling and holding bases, the AD conversion techniques with focuses in oversampled AD converters, the circuits that implementing SC and SI modulators and their influences, and finally a review of the nonidealities that involve the practice of project. Chapter 3 a comparative study is done between memory cells SC and SI. Based on a simplified model of small signals, the behavior analyzes on the signal-noise-ratio (SNR), power consumption and speed, providing indications of performance throughout the operating region of MOS transistors. Chapter 4 deals with the initial specifications for the development of a ΣΔ AD converter for a specific implementation. The s tudies and estimates lead to pre-design of the project's ultimate goal the creation of a ΣΔ modulator in the SC and SI techniques. In Chapter 5 is intended to make the measures and tests that establish the standards of comparison, the discussion of results and conclusions. Finally, in Chapter 6, an alternative proposal is presented based on an architecture that performs a sigma-delta modulator with low distortion, implemented with SI circuit. The final conclusions and contributions are presented in Chapter 7. / Circuitos de amostragem e retenção de sinais analógicos são comumente implementados com técnicas de chaveamento de capacitores (Switched Capacitor SC). Circuitos SC empregam o armazenamento de cargas em um capacitor linear para representar um sinal sob a forma de tensão. Amplificadores Operacionais (AmpOp s) são usados para transferir essa carga de um capacitor a outro, amostrando e retendo sinais analógicos em circuitos de malha fechada. Recentemente, uma outra técnica tem sido desenvolvida sem a necessidade de construção de capacitores lineares, tornando possíveis projetos compatíveis com processos de fabricação VLSI CMOS. Esta técnica, chamada de Switched Current (SI), caracteriza-se por processar os sinais sob a forma de correntes, sendo a operação de memorização implementada através da retenção de carga elétrica na porta de um transistor MOS na zona de saturação. A carga retida corresponde a uma tensão portafonte e, conseqüentemente, a uma corrente no transistor. Neste modelo, a excursão do sinal não é diretamente dependente da tensão de alimentação, mas dependente das correntes de polarização e de sinal. Isso torna o modelo atrativo para baixas tensões. A técnica não requer AmpOp s e implementação física de capacitores. A velocidade do circuito não é limitada por AmpOp s e seu produto ganho-banda, mas pelo projeto e processo de fabricação. Essa técnica ainda não está consolidada e sua performance ainda não é competitiva com os circuitos SC [1], Contudo, os circuitos SI tornam-se interessantes na medida em que constituem um campo aberto para futuras pesquisas e pela possibilidade de serem completamente implementados em processos de fabricação voltados a circuitos puramente digitais. Este trabalho inicia com um enquadramento do trabalho proposto, situando o leitor no contexto do estado da arte das tecnologias de fabricação e algumas implicações diretas que afetam circuitos analógicos. São apresentadas ainda nesta seção algumas implementações que servem para caracterizar o que está sendo feito recentemente em termos de conversores tipo Sigma Delta (ΣΔ). No Capítulo 2, faz-se o embasamento sobre as técnicas utilizadas no processo de amostragem e retenção utilizadas para conversão ADΣΔ e uma revisão das não idealidades que envolvem a prática de projeto. No Capítulo 3 é feito um estudo comparativo, entre células de memória SC e SI. Baseado em modelo simplificado de pequenos sinais, analisa-se o comportamento quanto à relação-sinal-ruido (SNR), ao consumo e à velocidade, fornecendo indicações de desempenho em toda região de funcionamento dos transistores MOS. No Capitulo 4 são abordadas as especificações iniciais ao desenvolvimento de um conversor ΣΔ para uma implementação específica. Os estudos e estimativas que conduzem a pré-concepção do projeto têm como objetivo final a geração de um modulador ΣΔ nas técnicas SC e SI. Nos Capítulos 5 efetuam-se as medidas e testes que estabelecem os padrões de comparação, a discussão dos resultados e conclusões. Por fim, no Capítulo 6, uma proposta alternativa é apresentada com base em uma arquitetura de modulador sigma-delta de baixa distorção, implementada em circuito SI. As conclusões e contribuições finais são apresentadas no capítulo 7.

Design step for Sigma-Delta ADC is introduced. Suitable solution for performance improvement of the original Sigma-Delta ADC, which meets new requirements on resolution of 16 bits and signal bandwidth 20-50 kHz is presented. Advantage of using multi-bit quantization and DEM DWA method reducing the linearity requirements of the internal feedback DAC is shown.

Wireless communication systems are based on frequency synthesizers that generate carrier signals, which are used to transmit information. Frequency synthesizers use voltage controlled oscillators (VCO) to produce the required frequencies within a specified period of time. In the process of generating frequency, the VCO and other electronic components such as amplifiers produce some unwanted short-term frequency variations, which cause frequency instability within the frequency of interest known as phase noise (PN). PN has a negative impact on the performance of the overall wireless communication system. A literature study conducted on this research reveals that the existing PN cancellation techniques have some limitations and drawbacks that require further attention. A new PN correction technique based on the combination of least mean square (LMS) adaptive filtering and single-loop single-bit Sigma Delta (SD) modulator is proposed. The new design is also based on the Cascaded Resonator Feedback (CRFB) architecture. The noise transfer function (NTF) of the architecture was formulated in way that made it possible to stabilize the frequency fluctuations within the in-band (frequency of interest) by locating its poles and zeros within the unit circle. The new design was simulated and tested on a commercially available software tool called Agilent Advanced Design System (ADS). Simulation results show that the new technique achieves better results when compared with existing techniques as it achieves a 104 dB signal-to-noise (SNR), which is an improvement of 9 dB when compared with the existing technique accessed from the latest publications. The new design also achieves a clean signal with minimal spurious tones within the inband with a phase noise level of -141 dBc/Hz (lower phase noise level by 28 dBc/Hz) when compared with the existing techniques. / Thesis (MEng)--University of Pretoria, 2017. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted

No description available.

<p>The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.</p><p>The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.</p>

State-of-the art electronic systems include ever more features and gather mixed-signal subsystems, possibly from different physical domains. At the same time, cost and development time are reduced; stressing the need for an efficient design flow for fast and reliable design. The present thesis contributes to the construction of an improved design flow supported by mixed-signal hardware description languages (HDL-AMS). In a hierarchical view, the electronic systems are recursively divided into subsystems, down to basic cells and transistor level. The typical design flow results of a top-down synthesis, from the system specifications to the physical realizations, and of a bottom-up validation, from the test of the basic cells up to the test of the system. To improve the link between the technological level and the basic cells, we develop a measurement-based analog ID card which aims to optimize the analog performance and the reliability at high temperature by enabling the choice of optimal process (bulk vs. partially-depleted silicon-on-insulator (SOI) vs. fully-depleted SOI), optimal devices (e.g. multi-threshold voltages process) and optimal bias (weak vs. moderate vs. strong inversion). In the present thesis, we deal with the following analog performance parameters: gain, gain-bandwidth product, MOSFET mismatch in weak inversion and harmonic distortion of MOSFETs in triode regime. We show that SOI transistors are still advantageous over bulk in deep-submicron CMOS technologies and that short-channel SOI transistors can safely be used for mixed-signal operation up to 250°C. The analog ID card can be included in the design flow supported by HDL-AMS. Behavioral models for the basic cells are developed using such languages and further assembled into a ÄÓ modulator with continuous-time integrators as it is a good candidate for low-power consumption and operation at high temperature. The related design issues are assessed using the behavioral models and a design optimization method is presented for a key building block, an active RC integrator with passive resistors.

The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.

This thesis presents the development of high resolution, wide dynamic range sigma-delta type readout circuits for capacitive MEMS accelerometers. Designed readout circuit employs fully differential closed loop structure with digital output, achieving high oversampling ratio and high resolution. The simulations of the readout circuit together with the accelerometer sensor are performed using the models constructed in Cadence and Matlab Simulink environments. The simulations verified the stability and proper operation of the accelerometer system. The sigma-delta readout circuit is implemented using XFab 0.6 &micro / m CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 &micro / g/&amp / #61654 / Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed &plusmn / 18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 &micro / g/&amp / #61654 / Hz of noise level and 74 &micro / g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/&ordm / C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.