However, the proposed receiver and channel selection scheme still suffer from the mismatches picked up during RF-to-IF conversion. Therefore, a system called phase and amplitude mismatch cancellers is adopted to deal with the problem. Existing implementations neglected several critical behaviors of the cancellers, and provide image rejection ratios (IRR) ranging from 50dB to 65dB only. These behaviors include (i) arithmetic underflow, (ii) angular obscurity and (iii) spurious intermodulation products (IMD) produced by cancellers. We analyzed them and established several design rules, by which a far better IRR of at least 82.5dB was achieved. The system makes the proposed receiver and channel selection method feasible. / In traditional receivers involving intermediate frequency (IF), two different RF channels, Signal and Image, are converted to the same IF and overlap with each other. The Signal is always wanted with the Image eliminated, so each RF LO frequency can only select one RF channel. By digital low-IF, the IF-to-baseband conversion can be configured so that either channel can be selected, then each RF LO frequency can select two RF channels. This enhanced channel selection scheme can effectively reduce the number of LO frequency locations by half as well as the requirements of RF PLL frequency synthesizer. An existing approach makes use of configurable sampling scheme to achieve the same aim, but its use of analog sampling circuits results in phase and amplitude mismatches, from which the performance of image rejection suffers. Digital low-IF does not have this problem, since no mismatches are introduced to the signals after digitization. / The proposed digital low-IF Weaver receiver, together with the enhanced channel selection scheme and the phase and amplitude mismatch cancellers, are demonstrated to be feasible by a multi-band multi-mode receiver prototype supporting GSM900 and WCDMA. / The receiver architecture proposed in this thesis makes use of Weaver architecture with digital low-IF. Its flexibility allows for any operations to be performed on the digitized signals, as well as the enhanced channel selection scheme proposed in this thesis. / Chan Pak Kee. / "September 2007." / Adviser: Chiu Sing Choy. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4924. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 152-162). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

by Tsang Yick Man, Steven. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 94-99). / ABSTRACT --- p.i / ACKNOWLEDGMENT --- p.ii / LIST OF GLOSSARY --- p.iii / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- What is the jitter ？ --- p.3 / Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ？ --- p.4 / Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4 / Chapter 2.1.1 --- Digital data problem --- p.7 / Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9 / Chapter 2.3 --- Waveform distortion --- p.12 / Chapter 2.4 --- Logic induced jitter --- p.17 / Chapter 2.4.1 --- Digital noise mechanisms --- p.20 / Chapter 2.4.2 --- Different types of D-type flop-flip chips are linked below for ease of comparison --- p.21 / Chapter 2.4.3 --- Ground bounce --- p.22 / Chapter 2.5 --- Power supply high frequency noise --- p.23 / Chapter 2.6 --- Interface Jitter --- p.25 / Chapter 2.7 --- Cross-talk --- p.28 / Chapter 2.8 --- Inter-Symbol-Interference (ISI) --- p.28 / Chapter 2.9 --- Baseline wander --- p.29 / Chapter 2.10 --- Noise jitter --- p.30 / Chapter 2.11 --- FIFO jitter reduction chips --- p.31 / Chapter 3 --- JITTER REDUCTION TECHNIQUES --- p.33 / Chapter 3.1 --- Why using two-stage phase-locked loop (PLL ) ？ / Chapter 3.1.1 --- The PLL circuit components --- p.35 / Chapter 3.1.2 --- The PLL timing specifications --- p.36 / Chapter 3.2 --- Analog phase-locked loop (APLL ) circuit usedin second stage --- p.38 / Chapter 3.3 --- All digital phase-locked loop (ADPLL ) circuit used in second stage --- p.40 / Chapter 3.4 --- ADPLL design --- p.42 / Chapter 3.4.1 --- "Different of K counter value of ADPLL are listed for comparison with M=512, N=256, Kd=2" --- p.46 / Chapter 3.4.2 --- Computer simulated results and experimental results of the ADPLL --- p.47 / Chapter 3.4.3 --- PLL design notes --- p.58 / Chapter 3.5 --- Different of the all digital Phase-Locked Loop (ADPLL ) and the analogue Phase-Locked Loop (APLL ) are listed for comparison --- p.65 / Chapter 3.6 --- Discrete transistor oscillator --- p.68 / Chapter 3.7 --- Discrete transistor oscillator circuit operation --- p.69 / Chapter 3.8 --- The advantage and disadvantage of using external discrete oscillator --- p.71 / Chapter 3.9 --- Background of using high-precision oscillators --- p.72 / Chapter 3.9.1 --- The temperature compensated crystal circuit operation --- p.73 / Chapter 3.9.2 --- The temperature compensated circuit design notes --- p.75 / Chapter 3.10 --- The discrete voltage reference circuit operation --- p.76 / Chapter 3.10.1 --- Comparing the different types of Op-amps that can be used as a voltage comparator --- p.79 / Chapter 3.10.2 --- Precaution of separate CMOS chips Vdd and Vcc --- p.80 / Chapter 3.11 --- Board level jitter reduction method --- p.81 / Chapter 3.12 --- Digital audio interface chips --- p.82 / Chapter 3.12.1 --- Different brand of the digital interface receiver (DIR) chips and clock modular are listed for comparison --- p.84 / Chapter 4. --- APPLICATION CIRCUIT BLOCK DIAGRAMS OF JITTER REDUCTION AND CLOCK RECOVERY --- p.85 / Chapter 5 --- CONCLUSIONS --- p.90 / Chapter 5.1 --- Summary of the research --- p.90 / Chapter 5.2 --- Suggestions for further development --- p.92 / Chapter 5.3 --- Instrument listing that used in this thesis --- p.93 / Chapter 6 --- REFERENCES --- p.94 / Chapter 7 --- APPENDICES --- p.100 / Chapter 7.1.1 --- Phase instability in frequency dividers / Chapter 7.1.2 --- The effect of clock tree on Tskew on ASIC chip / Chapter 7.1.3 --- Digital audio transmission----Why jitter is important? / Chapter 7.1.4 --- Overview of digital audio interface data structures / Chapter 7.1.5 --- Typical frequency Vs temperature variations curve of Quartz crystals / Chapter 7.2 --- IC specification used in these research project

Orientador: Cláudio Kitano / Banca: Ricardo Tokio Higuti / Banca: Regina Célia da Silva Barros Allil / Resumo: O grupo de estudos do Laboratório de Optoeletrônica (LOE) da FEIS-UNESP trabalha há vários anos na área de interferometria óptica. A expressão geral da transmissão (razão entre o retardo de fase e a tensão aplicada) de um modulador eletro-óptico de intensidades é idêntica à expressão do sinal fotodetectado na saída de um interferômetro de dois feixes. Em 2012, um novo método de detecção interferométrica de fase óptica foi desenvolvido no LOE, sendo denominado de método de segmentação do sinal amostrado (SSA). Este método é imune ao fenômeno de desvanecimento, é capaz de mensurar o valor da diferença de fase quase-estática entre os braços do interferômetro, consegue medir o tempo de atraso entre o estímulo e a resposta, é pouco sensível ao ruído eletrônico, apresenta excelente resolução, tem ampla faixa dinâmica, permite caracterizar dispositivos não-lineares e pode operar com uma grande variedade de sinais periódicos não-senoidais. Beneficiando-se dessas informações, promoveu-se uma adaptação do método SSA para fins de se implementar um sensor óptico de tensão (SOT) elevada, a base do efeito eletro-óptico linear em cristais de niobato de lítio. O trabalho desenvolvido nesta dissertação se insere nesta linha de pesquisa, porém, ao contrário de trabalhos pregressos realizados no LOE, onde o sinal fotodetectado era amostrado por um osciloscópio digital e processado em microcomputador, agora, empregam-se processadores digitais de sinais (DSPs) tanto para amostrar quanto processar o sinal. Operando-se com a placa eZdspF28335, de ponto-flutuante, foram executadas medições da forma de onda de sinais de alta tensão, em 60 Hz e com elevado conteúdo de harmônicas superiores. Desta forma, gráficos de linearidade (relação entre o retardo induzido versus tensão elétrica aplicada)... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: The Optoelectronic Laboratory (OEL) research group has been working for many years in the optical interferometry field. The general expression for the transmission (phase shift and drive voltage ratio) of an electro optic amplitude modulator is identical to the photo-detected signal at the output of a two-beam interferometer. In 2012, a new interferometry method for optical phase detection was developed at OEL, named Sampled Piece-Wise Signal (SPWS) method. This method, which is immune to fading, is used to measure the value of the quasi-static optical phase difference between the arms of the interferometer. The method has small influence from to electronic noise, provides excellent resolution, has a wide dynamic range, and allows the characterization of non-linear devices. Furthermore, the SPWS method is used to measure the time delay between stimulus and response and may operate with a wide variety of non-sinusoidal periodic signals. In this work the SPWS method is adjusted aiming the high voltage measurement by using an optical voltage sensor (OVT) based on the linear electro-optic effect in lithium niobate crystals. Unlike previous studies realized at OEL, where the photo-detected signal was acquired by a digital oscilloscope and processed with a microcomputer, a digital signal processor (DSPs) is employed for both signal acquisition and processing. Measurements of high voltage signal waveforms, at 60 Hz and with higher harmonic content, were performed using the eZdspF28335 card, with floating-point operation. Thus, OVT linearity (induced phase shift versus drive voltage) and frequency response curves were obtained. The spectrum of the high voltage signal was calculated, and hence, parameters such as THD (Total Harmonic Distortion) and IHD (Individual Harmonic Distortion) could be determined. Two different OVT configurations were tested... (Complete abstract click electronic access below) / Mestre

Excessive high-frequency jitter or low-frequency wander can create problems within synchronous transmission systems and must be kept within limits to ensure reliable network operation. The emerging Synchronous Optical NETwork (SONET) introduces additional challenges for jitter and wander attenuation equipment (called desynchronizers) when used to carry payloads from the existing Plesiochronous Digital Hierarchy (PDH), such as the DS3. The difficulty is primarily due to the large phase transients resulting from the pointer-based justification technique employed by SONET (called Pointer Justification Events or PJEs). While some previous desynchronization techniques consider the buffer level in their control actions, none has explicitly considered wander generation. Instead, compliance with jitter, wander, and buffer-size constraints have typically been met implicitly--through testing and tuning of the Phase Locked Loop (PLL) controller. We investigated a fuzzy/rule-based solution to this desynchronization/constraint-satisfaction problem. But rather than mapping the input state to an action, as is done in standard fuzzy logic, our controller maps a state and a candidate action to a desired result. In other words, this control paradigm employs prediction to evaluate which of a set of candidate actions would result in the "best" predicted performance. Before the controller could predict an action's affect on buffer and wander levels, appropriate models were required. The model of the buffer is simply the integral of the frequency difference between the input and output of the PLL, and a novel MTIE Constraint Envelope technique was developed to evaluate future wander performance. We show that a predictive knowledge-based controller is capable of achieving the following three objectives: (1) Reduce jitter implicitly by avoiding unnecessary frequency changes such that the jitter limits specified in relevant standards are met, (2) Explicitly satisfy both buffer-level and wander (MTIE) constraints by trading off performance in one to meet the hard limit of the other, (3) When both buffer-level and wander constraints are in danger of violation and cannot be satisfied simultaneously, maintain the preferred constraint by sacrificing the other. We also show that the computation required for this control algorithm is easily within the reach of modern microprocessors.

This thesis studies the problem of estimating the interior structure of a collapsed building using embedded Ultra-Wideband (UWB) radios as sensors. The two major sensing problems needed to build the mapping system are determining wall type and wall orientation. We develop sensing algorithms that determine (1) load-bearing wall composition, thickness, and location and (2) wall position within the indoor cavity. We use extensive experimentation and measurement to develop those algorithms. In order to identify wall types and locations, our research approach uses Received Signal Strength (RSS) measurement between pairs of UWB radios. We create an extensive database of UWB signal propagation data through various wall types and thicknesses. Once the database is built, fingerprinting algorithms are developed which determine the best match between measurement data and database information. For wall mapping, we use measurement of Time of Arrival (ToA) and Angle of Arrival (AoA) between pairs of radios in the same cavity. Using this data and a novel algorithm, we demonstrate how to determine wall material type, thickness, location, and the topology of the wall. Our research methodology utilizes experimental measurements to create the database of signal propagation through different wall materials. The work also performs measurements to determine wall position in simulated scenarios. We ran the developed algorithms over the measurement data and characterized the error behavior of the solutions. The experimental test bed uses Time Domain UWB radios with a center frequency of 4.7 GHz and bandwidth of over 3.2 GHz. The software was provided by Time Domain as well, including Performance Analysis Tool, Ranging application, and AoA application. For wall type identification, we use the P200 radio. And for wall mapping, we built a special UWB radio with both angle and distance measurement capability using one P200 radio and one P210 radio. In our experimental design for wall identification, we varied wall type and distance between the radios, while fixing the number of radios, transmit power and the number of antennas per radio. For wall mapping, we varied the locations of reference node sensors and receiver sensors on adjoining and opposite walls, while fixing cavity size, transmit power, and the number of antennas per radio. As we present in following chapters, our algorithms have very small estimation errors and can precisely identify wall types and wall positions.

Because the voltage amplitude of a heart beat is small compared to the amplitude of exponential noise, pacemakers have difficulty registering the responding heart beat immediately after a pacing pulse. This thesis investigates use of digital filters, an inverse filter and a lowpass filter, to eliminate the effects of exponential noise following a pace pulse. The goal was to create a filter which makes recognition of a haversine wave less dependent on natural subsidence of exponential noise. Research included the design of heart system, pacemaker, pulse generation, and D sensor system simulations. The simulation model includes the following components: \ • Signal source, A MA TLAB generated combination of a haversine signal, exponential noise, and myopotential noise. The haversine signal is a test signal used to simulate the QRS complex which is normally recorded on an ECG trace as a representa tion of heart function. The amplitude is approximately 10 mV. Simulated myopotential noise represents a uniformly distributed random noise which is generated by skeletal muscle tissue. The myopotential noise has a frequency spectrum extending from 70 to 1000Hz. The amplitude varies from 2 to 5 mV. Simulated exponential noise represents the depolarization effects of a pacing pulse as seen at the active cardiac lead. The amplitude is about -1 volt, large in comparison with the haversine signal. • AID converter, A combination of sample & hold and quantizer functions translate the analog signal into a digital signal. Additionally, random noise is created during quantization. • Digital filters, An inverse filter removes the exponential noise, and a lowpass filter removes myopotential noise. • Threshold level detector, A function which detects the strength and amplitude of the output signal was created for robustness and as a data sampling device. The simulation program is written for operation in a DOS environment. The program generates a haversine signal, myopotential noise (random noise), and exponential noise. The signals are amplified and sent to an AID converter stage. The resultant digital signal is sent to a series of digital filters, where exponential noise is removed by an inverse digital filter, and myopotential noise is removed by the Chebyshev type I lowpass digital filter. The output signal is "detected" if its waveform exceeds the noise threshold level. To determine what kind of digital filter would remove exponential noise, the spectrum of exponential noise relative to a haversine signal was examined. The spectrum of the exponential noise is continuous because the pace pulse is considered a non-periodic signal (assuming the haversine signal occurs immediately after a pace pulse). The spectrum of the haversine is also continuous, existing at every value of frequency co. The spectrum of the haversine is overlapped by the spectrum of and amplitude of the exponential, which is several orders of magnitude larger. The exponential cannot be removed by conventional filters. Therefore, an inverse filter approach is used to remove exponential noise. The transfer function of the inverse filter of the model has only zeros. This type of filter is called FIR, all-zero, non recursive, or moving average. Tests were run using the model to investigate the behavior of the inverse filter. It was found that the haversine signal could be clearly detected within a 5% change in the time constant of the exponential noise. Between 5% and 15% of change in the time constant, the filtered exponential amplitude swamps the haversine signal. The sensitivity of the inverse filter was also studied: when using a fixed exponential time constant but changing the location of the transfer function, the effect of the exponential noise on the haversine is minimal when zeros are located between 0.75 and 0.85 of the unit circle. After the source signal passes the inverse filter, the signal consists only of the haversine signal, myopotential noise, and some random noise introduced during quantization. To remove these noises, a Chebyshev type I lowpass filter is used.

Component values of integrated filters vary considerably due to· manufacturing tolerances and environmental changes. Thus it is of major importance that the components of an integrated filter be electronically tunable. The method explored in this thesis is the transconductance-C-method. A method of realizing higher-order filters is to use a cascade structure of second-order filters. In this context, a method of tuning second-order filters becomes important The research objective of this thesis is to determine if the Neural Network methodology can be used to facilitate the filter tuning process for a second-order filter (realized via the transconductance-C-method). Since this thesis is, at least to the knowledge of the author, the first effort in this direction, basic principles of filters and of Neural Networks [1-22] are presented. A control structure is proposed which comprises three parts: the filter, the Neural Network, and a digital spectrum analyzer. The digital spectrum analyzer sends a test signal to the filter and measures the magnitude of the output at 49 frequency samples. The Neural Network part includes a memory that stores the 49 sampled values of the nominal spectrum. ·A comparator subtracts the latter values from the measured (actual) values, and feeds them as input to the Neural Network. The outputs of the Neural Network are the values of the percentage tuning amount The adjusting device, which is envisioned as a component of the filter itself, translates the output of the Neural Network to adjustments in the value of the filter's transconductances. Experimental results provide a demonstration that the Neural Network methodology can be usefully applied to the above problem context. A feedforward, singlehidden layer Backpropagation Network reduces the manufacturing errors of up to 85% for the pole frequency and of up to 41% for the quality factor down to less than approximately 5% each. It is demonstrated that the method can be iterated to further reduce the error.

With the advance of the VLSI technology, the FFT algorithm has been pushed further in solving the multidimensional array signal processing in real time. Many DSP chip users have tried to find ways to improve addressing huge data in multidimension systems with minimum cost and maximum performance. However, there is no efficient method to address data for 1-D to M-D FFTs. A methodology has been defined to conquer the addressing problem ofM-D FFT. It is well known that the twiddle factor matrix of Discrete Fourier Transform (DFT) can be recursively factored into basic butterfly stage matrices. The matrix can be factored into three matrices practically specifying the input data, twiddle factor, and output data sequence of the Fast Fourier Transform (FFT). The equivalent relationship of these matrices will be introduced. The equivalent relationship for a variety of the FFT algorithms can be obtained by equivalent transformations. Furthermore, the multidimensional (M-D) FFT can be represented by the same vector-matrix form as the one-dimensional (1-D) FFT. In addition, the addressing sequences of the 1-D FFT is a subset of the M-D FFT. Therefore, the signal flow graph of the 1-D FFT can be used to describe that of the M-D FFT and all M-D indexing can be implemented by 1-D indexing. Finally, this unified indexing approach was implemented into the WinDSP software simulator. Examples of M-D FFTs implemented with the unified indexing method are simulated on the WinDSP and the computation performance were analyzed. From the benchmark analysis, the 2-D FFT applications implemented with unified methodology use less instructions and the execution time is almost two times faster than the traditional method. WinDSP is a software simulator that simulates the functional characteristics of Sharp LH9124/LH9320 DSP chip set. It intended to manage the complete development of DSP applications, from conceptualization and experimentation, to verification of unified indexing for 1-D to M-D FFT. It is also intended for system development, where hardware can be implemented for the design.

The 24-bit Motorola DSP56001 processor will be used in combination with the DSP56ADC16 and the PCM-56 to design a good FIR compensation filter. Our objective is to digitize the input analog signal, and to compensate for the attenuation in the magnitude response of the digital sine wave. Two different experiments will be conducted, a hands on approach, and a simulation program. The first one will be realized directly, using the DSP system. We will determine the magnitude response of the system, and then deduce the coefficients of the FIR sin(x)/x filter. A look up table will store those values which will be fetched by the DSP program. With a minimum set of instructions we will generate a new digital output sequence after a N-point circular convolution is performed. The output signal is a good reconstruction of the input signal at frequencies below 22 Khz. However, a second experiment will be needed to improve this FIR sin(x)/x compensation filter, because we are not able to go beyond a 300-point impulse sequence. After that value (300-point), the time that each value is read and is ready to be processed by the DSP56001 becomes smaller than the time each instruction in the DSP program is executed and written to the PCM-56 via the SSI register. To be able to expand our experiment, we need to write a simulation program. A simulation program of the previous experiment, which take as input the measured magnitude response of the system. The challenge will be to find ways to map the frequency domain, by using the maximum value of each linear convolution sequence, with a finite input sequence. A step by step approach will be drawn until our final objective is reached. Our final step will be, to increase the number of sampling point in the frequency domain and will be to demonstrate that the result of the simulated program value will coincide with our objective, which is to compensate for the attenuation of the magnitude response of the system. By increasing the sampling frequency we will eventually obtain a good compensation filter.

Abstract not available