Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017. / The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.

Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. / Includes bibliographical references (leaves 99-100). / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be individually reconfigured while the remainder of the device continues to operate. This document describes the design, implementation, simulation, and benchmarking of a five-socket modular DSP architecture and compares the results to the performance of alternative digital signal processing methods, particularly that of software DSP subroutines run on a PowerPC processor. The result is a highly flexible architecture that supports the use of timing verified hardware subroutines that could be partially reconfigured onto the FPGA within 3ms. The highly parallel processing power of the FPGA design yields a performance of 5.825 billion multiply and accumulate operations per second while simulated running at 72.8MHz, more than 76 times faster than similar calculations measured on a MPC7410 processor. / by Justin D. McBride. / M.Eng.and S.B.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Bibliography: leaf 94. / by Esteban José Peynado Sánchez. / M.S.

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Paul Moroney. / Ph.D.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Robert A. Ulichney. / M.S.

This work investigates two different digital signal processing (DSP) approaches that rely on signal-derived timing: continuous-time (CT) DSP and variable-rate DSP. Both approaches enable designs of energy-efficient signal processing systems by relating their operation rates to the input activity. The majority of this thesis focuses on CT-DSP, whose operations are completely digital in CT, without the use of a clock. The spectral features of CT digital signals are analyzed first, demonstrating a general pattern of the quantization noise spectrum added in CT amplitude quantization. Then the focus is narrowed to the investigations of the system characteristics and architecture of CT digital infinite-impulse-response (IIR) filters, which are barely studied in the previous work on this topic. This thesis discusses and addresses previously unreported stability issue in CT digital IIR filters with the presence of delay-line mismatches and proposes an innovative method to design high-order CT digital IIR filters with only two tap delays. Introducing an event detector allows the operation rate of a CT digital IIR filter to closely track the input activity even though it is a feedback system. For the first time, the filtered CT digital signal is converted to a synchronous digital signal. This facilitates integrating the CT digital filter and conventional discrete-time systems and expands the applications of the former. This discussion uses a computationally efficient interpolation filter to improve the signal accuracy of the synchronous digital output. On the circuit level, a new delay-cell design is introduced. It ensures low jitter, good matching, robust communication with adjacent circuits and event-independent delay. An integrated circuit (IC) with all these ideas adopted was fabricated in a TSMC 65 nm LP CMOS process. It is the first IC implementation of a CT digital IIR filter. It can process signals with a data rate up to 20 MHz. Thanks to the IIR response and the 16-bit resolution used in the system, the implemented filter can achieve a frequency response much more versatile and accurate than the CT digital filters in prior art. The implemented system features an agile power adaptive to input activity, varying from 2.32mW (full activity) to 40μW (idle) with no power-management circuitry. The second part of the thesis discusses a variable-rate DSP capable of processing samples with a variable sampling rate. The clock rate in the variable-rate DSP tracks the input sampling rate. Compared to a fixed-rate DSP, the proposed system has a lower output data rate and hence is more computationally efficient. A reconstruction filter with a variable cutoff frequency is used to reconstruct the output. The signal-to-noise ratio remains fixed when the sampling rate changes.

Kwok Yan-lun Andy. / Thesis submitted in: November 2004. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 133-137). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgements --- p.iii / List of Figures --- p.vii / List of Tables and Examples --- p.x / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Motivation --- p.1 / Chapter 1.2. --- Objective and Approach --- p.4 / Chapter 1.3. --- Thesis Organization --- p.5 / Chapter 2. --- Related Work --- p.7 / Chapter 2.1. --- Coverage --- p.7 / Chapter 2.2. --- ASIP Design Methodologies --- p.8 / Chapter 2.3. --- Asynchronous Technology on Processors --- p.12 / Chapter 2.4. --- Summary --- p.14 / Chapter 3. --- Asynchronous Design Methodology --- p.15 / Chapter 3.1. --- Overview --- p.15 / Chapter 3.2. --- Asynchronous Design Style --- p.17 / Chapter 3.2.1. --- Micropipelines --- p.17 / Chapter 3.2.2. --- Fine-grain Pipelining --- p.20 / Chapter 3.2.3. --- Globally-Asynchronous Locally-Synchronous (GALS) Design --- p.22 / Chapter 3.3. --- Advantages of GALS in ASIP Design --- p.27 / Chapter 3.3.1. --- Reuse of Synchronous and Asynchronous IP --- p.27 / Chapter 3.3.2. --- Fine Tuning of Performance and Power Consumption --- p.27 / Chapter 3.3.3. --- Synthesis-based Design Flow --- p.28 / Chapter 3.4. --- Design of GALS Asynchronous Wrapper --- p.28 / Chapter 3.4.1. --- Handshake Protocol --- p.28 / Chapter 3.4.2. --- Pausible Clock Generator --- p.29 / Chapter 3.4.3. --- Port Controllers --- p.30 / Chapter 3.4.4. --- Performance of the Asynchronous Wrapper --- p.33 / Chapter 3.5. --- Summary --- p.35 / Chapter 4. --- Platform Based ASIP Design Methodology --- p.36 / Chapter 4.1. --- Platform Based Approach --- p.36 / Chapter 4.1.1. --- The Definition of Our Platform --- p.37 / Chapter 4.1.2. --- The Definition of the Platform Based Design --- p.37 / Chapter 4.2. --- Platform Architecture --- p.38 / Chapter 4.2.1. --- The Nature of DSP Algorithms --- p.38 / Chapter 4.2.2. --- Design Space of Datapath Optimization --- p.46 / Chapter 4.2.3. --- Proposed Architecture --- p.49 / Chapter 4.2.4. --- The Strategy of Realizing an Optimized Datapath --- p.51 / Chapter 4.2.5. --- Pipeline Organization --- p.59 / Chapter 4.2.6. --- GALS Partitioning --- p.61 / Chapter 4.2.7. --- Operation Mechanism --- p.63 / Chapter 4.3. --- Overall Design Flow --- p.67 / Chapter 4.4. --- Summary --- p.70 / Chapter 5. --- Design of the ASIP Platform --- p.72 / Chapter 5.1. --- Design Goal --- p.72 / Chapter 5.2. --- Instruction Fetch --- p.74 / Chapter 5.2.1. --- Instruction fetch unit --- p.74 / Chapter 5.2.2. --- Zero-overhead loops and Subroutines --- p.75 / Chapter 5.3. --- Instruction Decode --- p.77 / Chapter 5.3.1. --- Instruction decoder --- p.77 / Chapter 5.3.2. --- The Encoding of Parallel and Complex Instructions --- p.80 / Chapter 5.4. --- Datapath --- p.81 / Chapter 5.4.1. --- Base Functional Units --- p.81 / Chapter 5.4.2. --- Functional Unit Wrapper Interface --- p.83 / Chapter 5.5. --- Register File Systems --- p.84 / Chapter 5.5.1. --- Memory Hierarchy --- p.84 / Chapter 5.5.2. --- Register File Organization --- p.85 / Chapter 5.5.3. --- Address Generation --- p.93 / Chapter 5.5.4. --- Load and Store --- p.98 / Chapter 5.6. --- Design Verification --- p.100 / Chapter 5.7. --- Summary --- p.104 / Chapter 6. --- Case Studies --- p.105 / Chapter 6.1. --- Objective --- p.105 / Chapter 6.2. --- Approach --- p.105 / Chapter 6.3. --- Based versus Optimized --- p.106 / Chapter 6.3.1. --- Matrix Manipulation --- p.106 / Chapter 6.3.2. --- Autocorrelation --- p.109 / Chapter 6.3.3. --- CORDIC --- p.110 / Chapter 6.4. --- Optimized versus Advanced Commercial DSPs --- p.113 / Chapter 6.4.1. --- Introduction to TMS320C62x and SC140 --- p.113 / Chapter 6.4.2. --- Results --- p.115 / Chapter 6.5. --- Summary --- p.116 / Chapter 7. --- Conclusion --- p.118 / Chapter 7.1. --- When ASIPs encounter asynchronous --- p.118 / Chapter 7.2. --- Contributions --- p.120 / Chapter 7.3. --- Future Directions --- p.121 / Chapter A --- Synthesis of Extended Burst-Mode Asynchronous Finite State Machine --- p.122 / Chapter B --- Base Instruction Set --- p.124 / Chapter C --- Special Registers --- p.127 / Chapter D --- Synthesizable Model of GALS Wrapper --- p.130 / Reference --- p.133

This work explores the process of model-based classification of speech audio signals using low-level feature vectors. The process of extracting low-level features from audio signals is described along with a discussion of established techniques for training and testing mixture model-based classifiers and using these models in conjunction with feature selection algorithms to select optimal feature subsets. The results of a number of classification experiments using a publicly available speech database, the Berlin Database of Emotional Speech, are presented. This includes experiments in optimizing feature extraction parameters and comparing different feature selection results from over 700 candidate feature vectors for the tasks of classifying speaker gender, identity, and emotion. In the experiments, final classification accuracies of 99.5%, 98.0% and 79% were achieved for the gender, identity and emotion tasks respectively. / by Chris Thoman. / Thesis (M.S.C.S.)--Florida Atlantic University, 2009. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2009. Mode of access: World Wide Web.

Fan Chun Wah. / "March 2002." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (p. [140]-148). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

In practice, the application and extension of the ICA model depend on the problem and the data to be investigated. We finally focus on GARCH models in finance, and show that estimation of univariate or multivariate GARCH models is actually a nonlinear ICA problem; maximizing the likelihood is equivalent to minimizing the statistical dependence in standardized residuals. ICA can then be used for factor extraction in multivariate factor GARCH models. We also develop some extensions of ICA for this task. These techniques for extracting factors from multivariate return series are compared both theoretically and experimentally. We find that the one based on conditional decorrelation between factors behaves best. / In this thesis, first we consider the problem of source separation of post-nonlinear (PNL) mixtures, which is an extension of ICA to the nonlinear mixing case. With a large number of parameters, existing methods are computation-demanding and may be prone to local optima. Based on the fact that linear mixtures of independent variables tend to be Gaussian, we develop a simple and efficient method for this problem, namely extended Gaussianization. With Gaussianization as preprocessing, this method approximates each linear mixture of independent sources by the Cornish-Fisher expansion with only two parameters. Inspired by the relationship between the PNL mixing model and the Wiener system, extended Gaussianization is also proposed for blind inversion of Wiener systems. / Independent component analysis (ICA) is a recent and powerful technique for recovering latent independent sources given only their mixtures. The basic ICA model assumes that sources are linearly mixed and mutually independent. / Next, we study the subband decomposition ICA (SDICA) model, which extends the basic ICA model to allow dependence between sources by assuming that only some narrow-band source sub-components are independent. In SDICA, it is difficult to determine the subbands of source independent sub-components. We discuss the feasibility of performing SDICA in an adaptive manner. An adaptive method, called band selective ICA, is then proposed for this task. We also investigate the relationship between overcomplete ICA and SDICA and show that band selective ICA can solve the overcomplete ICA problems with sources having specific frequency localizations. Experimental results on separating images of human faces as well as artificial data are presented to verify the powerfulness of band selective ICA. / Zhang Kun. / "July 2005." / Adviser: Lai-Wan Chan. / Source: Dissertation Abstracts International, Volume: 67-07, Section: B, page: 3925. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (p. 218-234). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.