published_or_final_version / Electrical Engineering / Master / Master of Philosophy

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The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions. / Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.

As modern integrated-circuit (IC) technology advances, the level of integration increases, and so too does the clock speed of on-chip signals. As a result, signal integrity has become a major issue on which the circuit performance is largely based. Clock jitter is one of the main issues of signal integrity, and it has become one of the most important circuit limitations. / While extensive research is on-going to reduce clock jitter in ICs, researchers have also been actively involved in discovering ways to characterize it through applications of new time measurement units, or TMUs for short. A number of TMUs have been designed with resolutions down to the picosecond range, among which the time-to-voltage converter (TVC) is a very popular family of circuits used for making highly precise and accurate time measurements. These circuits are popular due to their excellent linearity properties and their ease of fabrication. Nonetheless, these circuits suffer from metastability issues, limiting the lower end of their measurement range. / This thesis first reviews the past TMU circuits, and then presents a TVC architecture that solves the metastability problem. In addition, pipelined operation is added to further increase the throughput of the design. The resolution of the TVC is made adjustable such that it can be used as a stand-alone TMU for different types of applications. The proposed TVC is both verified in simulation and experimentally using a custom designed circuit in a standard 0.18 microm CMOS process supplied by TSMC. Finally, a calibration method is included to further improve the linearity of the overall design.

The application of digital signal processing to radio communications has come of age with the advent of low power, high speed microprocessors and over the past five years, various transceiver architectures, utilizing this new technology have been extensively researched. Due to the flexible nature of a software based transceiver, a myriad of possible applications exist and currently the emphasis is on the development of suitable algorithms. The principal aim of this research is the derivation of optimized digital signal processing algorithms applicable to three separate areas of radio communications. Optimized, as used by the author within this dissertation, implies a reasonable compromise between performance, complexity and numerical processing efficiency. This compromise is necessary since the algorithms are applied to a portable transceiver where power consumption, size and weight are limited. The digital signal processing algorithms described by this research is as follows:- 1. The derivation and assessment of a multirate speech amplitude modulation demodulator which exhibits low distortion (typically less than 2%) for a wide range of modulation indices, carrier frequency offsets and deviations. The demodulator is processing efficient and requires only five multiplications and five decisions for every output sample. 2. The derivation and assessment of a low sampling rate speech frequency modulation demodulator for signals whose bandwidth exceed quarter the sampling frequency. The demodulator exhibits low distortion (typically less than 2%) and is processing efficient requiring eighteen multiplications and three decisions for every output sample. 3. The derivation and assessment of a multirate single-sideband suppressed carrier automatic frequency control system which is a combination of a simple second order adaptive line enhancer and a digital phase-locked loop. The processing efficient automatic frequency control system is suited for low signal to noise power conditions, in both stationary and mobile communication channels. / Thesis (Ph.D.)-University of Natal, Durban, 1992.

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