SiC is an attractive material since it has remarkable properties. For several years efforts have been put primarily in electronic applications. High power and high frequency devices can be fabricated on SiC due to its wide band gap, high breakdown field and high thermal conductivity. SiC devices can be used in harsh environment since its operation temperature is significantly high (about 1200 ). SiC bulk growth has been improved by seeded physical vapour transport (PVT) during last decades. However, the quality and doping concentration of SiC bulk are not good enough to be used as an active layer for devices. SiC epilayer growth by chemical vapour deposition (CVD) was established in the last three decades. Only about 5 µm/h growth rate is achieved by CVD with a standard process. Long deposition time is required to grow ≥100µm thick epilayer for high voltage devices. The main problem in standard CVD is the formation of silicon (Si) droplets due to supersaturation of Si-species on the growth surface or in the gas-phase, which is detrimental for devices performance. To solve the problem of Si-droplets, chloride-based CVD was introduced. Chlorinated species can dissolve the silicon aggregates through the formation of strong bonds to silicon species compared to Si-Si bonds. Typical chlorinated precursors are hydrogen chloride (HCl) and methyltrichlorosilane (MTS). In this thesis study, HCl was mainly used as chlorinated precursors. Distinct chlorinated precursors result in different chemical reactions which affect the epilayer growth appreciably. The Cl/Si ratio, which is the ratio of the amount of chlorinated precursors to silicon precursors, is a very critical growth parameter for morphology, growth rate and background doping concentration. The C/Si ratio and Si/H2 ratio also affect the epilayer growth appreciably. Besides, growth temperature, growth pressure and temperature ramp up condition are other important growth parameters. In the CVD reaction chamber, the temperature profile and gas species distribution are not uniform along the whole susceptor length, which leads to different thickness of epilayer, morphology and doping concentration at different area of the reaction chamber. The polarity and off-angle of substrates can bring about complete different grown epilayers. Epitaxial defects are mainly replicated from the substrate. Therefore, the quality of substrates is very important as well. Deep energy levels can be introduced by adding transition metal such as vanadium (V), chromium (Cr) or tungsten (W). There are some limits which are needed to be overcome for a complete development of SiC. 4” SiC wafers are commercially available on the market, larger diameter would be very useful for the industrial development of SiC. High growth rate and good quality with controlled uniformity are desired for electronic applications. In this thesis, the influences of growth parameters such as C/Si and Cl/Si ratios, comparison between different precursors, growth condition in different areas of reaction chamber and effects of substrate polarity are discussed. Intentional incorporation of tungsten atoms is investigated by deep-level transient spectroscopy measurement and thermodynamic analysis.

In this thesis work, it was aimed to optimize the conditions to produce silicon carbide (SiC), from rice husks from Turkish Thrace Region, via pyrolysis. Rice husks, coked at 500oC, were high energy ball-milled prior to pyrolysis, in order to investigate the effects of ball-milling on pyrolysis temperature, pyrolysis time and morphology of the SiC produced. Samples of rice husks subjected to different ball milling conditions, were pyrolyzed at temperatures varying from 1500oC to 1600oC and for times varying from &frac12 / hour to 2 hours. Results of experiments showed that, ball-milling reduced the pyrolysis temperature and pyrolysis time to some extent. It was also experimentally shown that ball-milling favored the formation of SiC particles rather than formation of SiC whisker.

This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs. / © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.QC 20111220

In this thesis, various issues regarding normally-ON silicon carbide (SiC)Junction Field-Effect Transistors (JFETs) are treated. Silicon carbide powersemiconductor devices are able to operate at higher switching frequencies,higher efficiencies, and higher temperatures compared to silicon counterparts.From a system perspective, these three advantages of silicon carbide can determinethe three possible design directions: high efficiency, high switchingfrequency, and high temperature.The structure designs of the commercially-available SiC power transistorsalong with a variety of macroscopic characteristics are presented. Apart fromthe common design and performance problems, each of these devices suffersfrom different issues and challenges which must be dealt with in order to pavethe way for mass production. Moreover, the expected characteristics of thefuture silicon carbide devices are briefly discussed. The presented investigationreveals that, from the system point-of-view, the normally-ON JFET isone of the most challenging silicon carbide devices. There are basically twoJFET designs which were proposed during the last years and they are bothconsidered.The state-of-the-art gate driver for normally-ON SiC JFETs, which wasproposed a few years ago is briefly described. Using this gate driver, theswitching performance of both Junction Field-Effect Transistor designs wasexperimentally investigated.Considering the current development state of the available normally-ONSiC JFETs, the only way to reach higher current rating is to parallel-connecteither single-chip discrete devices or to build multichip modules. Four deviceparameters as well as the stray inductances of the circuit layout might affectthe feasibility of parallel connection. The static and dynamic performance ofvarious combinations of parallel-connected normally-ON JFETs were experimentallyinvestigated using two different gate-driver configurations.A self-powered gate driver for normally-ON SiC JFETs, which is basicallya circuit solution to the “normally-ON problem” is also shown. This gatedriver is both able to turn OFF the shoot-through current during the startupprocess, while it also supplies the steady-state power to the gate-drivecircuit. From experiments, it has been shown that in a half-bridge converterconsisting of normally-ON SiC JFETs, the shoot-through current is turnedOFF within approximately 20 μs.Last but not least, the potential benefits of employing normally-ON SiCJFETs in future power electronics applications is also presented. In particular,it has been shown that using normally-ON JFETs efficiencies equal 99.8% and99.6% might be achieved for a 350 MW modular multilevel converter and a40 kVA three-phase two-level voltage source converter, respectively.Conclusions and suggestions for future work are given in the last chapterof this thesis. / I denna avhandling behandlas olika aspekter av normally–ON junction–field–effect–transistorer (JFETar) baserade på kiselkarbid (SiC). Effekthalvledarkomponenteri SiC kan arbeta vid högre switchfrekvens, högre verkningsgradoch högre temperatur än motsvarigheterna i kisel. Ur ett systemperspektivkan de tre nämnda fördelarna användas i omvandlarkonstruktionen för attuppnå antingen hög verkningsgrad, hög switchfrekvens eller hög temperaturtålighet.Såväl halvledarstrukturen som de makroskopiska egenskaperna för kommersiellttillgängliga SiC–transistorer presenteras. Bortsett från de vanligakonstruktions–och prestandaproblemen lider de olika komponenterna av ettantal tillkortakommanden som måste övervinnas för att bana väg för massproduktion.Även framtida SiC–komponenter diskuteras.Ur ett systemperspektiv är normally-ON JFETen en av de mest utmanandeSiC-komponenterna. De två varianter av denna komponent som varittillgängliga de senaste åren har båda avhandlats.State–of–the–art–drivdonet för normally-ON JFETar som presenteradesför några år sedan beskrivs i korthet. Med detta drivdon undersöks switchegenskapernaför båda JFET-typerna experimentellt.Vid beaktande av det aktuella utvecklingsstadiet av de tillgängliga normally–ON JFETarna i SiC, är det möjligt att uppnå höga märkströmmar endastom ett antal single–chip–komponenter parallellkopplas eller om multichipmodulerbyggs. Fyra komponentparametrar samt strö-induktanser för kretsenkan förutses påverka parallellkopplingen. De statiska och dynamiska egenskapernaför olika kombinationer av parallellkopplade normally-ON JFETarundersöks experimentellt med två olika gate–drivdonskonfigurationer.Ett självdrivande gate-drivdon för normally-ON JFETar presenteras också.Drivdonet är en kretslösning till “normally–ON–problemet”. Detta gatedrivdonkan både stänga av kortslutningsströmmen vid uppstart och tillhandahållaströmförsörjning vid normal drift. Med hjälp av en halvbrygga medkiselkarbidbaserade normally–ON JFETar har det visats att kortslutningsströmmenkan stängas av inom cirka 20 μs.Sist, men inte minst, presenteras de potentiella fördelarna med användningenav SiC-baserade normally-ON JFETar i framtida effektelektroniskatillämpningar. Speciellt visas att verkningsgrader av 99.8% respektive 99.5%kan uppnås i fallet av en 350 MW modular multilevel converter och i en40 kVA tvånivåväxelriktare. Sista kaplitet beskriver slutsatser och föreslagetframtida arbete. / <p>QC 20130527</p>

Nanocrystalline beta-silicon carbide (ß-SiC) was synthesized at relatively low temperature (<1300C) by carbothermal reduction (CTR) reaction in fine scale carbon/silica mixtures. The fine scale mixing of the reactants (i.e., carbon and silica) was achieved by solution-based processing and subsequent heat treatment. The mechanism of the CTR reaction in the current system was investigated from different aspects. The condensates of the volatile species generated during the CTR reaction was collected and analyzed. The results supported previous investigations which suggested that the CTR reaction is a multi-step process that involves silicon monoxide (SiO) vapor as a reaction intermediate. The kinetics of the CTR reaction was investigated by isothermal weight loss study and by the study which determined the amount of SiC formed via quantitative X- ray diffraction (QXRD) analysis. The results of kinetic study were consistent with the "shrinking-core" model, in which the reaction between SiO vapor and carbon at the carbon surface to produce SiC is the rate-controlling step. In addition, several techniques, including XRD, gas adsorption analysis, laser diffraction particle size analysis, SEM, TEM, etc., had been used to study the structural evolutions of the reaction product of CTR. It was demonstrated that the evolutions of product structure characteristics such as crystallite size, specific surface area, specific pore volume, pore size distribution, particle size distribution, and powder morphology, etc. were consistent with each other and provided support to the reaction mechanism proposed.

The goal of this research is to investigate how to deposit SiC material from methyltrichlorosilane (MTS) and H2 using the LCVD technique. Two geometries were targeted, fiber and line. In order to eliminate the volcano effect for LCVD-SiC deposition, a thermodynamics model was developed to check the feasibility and determine the deposition temperature ranges that will not cause the volcano effect, theoretically. With the aid of the thermodynamic calculations and further experimental explorations, the processing conditions for SiC fibers and lines without volcano effect were determined. The experimental relationships between the volcano effect and the deposition temperatures were achieved. As for the SiC lines, the deposition conditions for eliminating volcano effect were determined with the help of surface response experiment and the experience of SiC fiber depositions. The LCVD process of SiC deposition was characterized by performing a kinetic study of SiC deposition. The deposits were characterized by the means of polishing, chemical etching, and SEM technique. A coupled thermal and structural model was created to calculate the thermal residual stress present in the deposits during the deposition process and during the cooling process. Laser heating of LCVD system was studied by developing another model. The transient temperature distribution within the fiber and substrate was obtained. The theoretical relationships between the laser power and the fiber heights for maintaining constant deposition temperatures were achieved.

In this work, the development of theoretically-dense, clean grain boundary, high hardness solid-state sintered silicon carbide (SiC) armor was pursued. Boron carbide and graphite (added as phenolic resin to ensure the carbon is finely dispersed throughout the microstructure) were used as sintering aids. SiC batches between 0.25-4.00 wt.% carbon were mixed and spray dried. Cylindrical pellets were pressed at 13.7 MPa, cold-isostatically pressed (CIP) at 344 MPa, sintered under varying sintering soaking temperatures and heating rates, and varying post hot-isostatic pressing (HIP) parameters. Carbon additive amounts between 2.0-2.5 wt.% (based on the resin source), a 0.36 wt.% B4C addition, and a 2050°C sintering soak yielded parts with high sintering densities (~95.5-96.5%) and a fine, equiaxed microstructure (d50 = 2.525 µm). A slow ramp rate (10°C/min) prevented any occurrence of abnormal grain growth. Post-HIPing at 1900°C removed the remaining closed porosity to yield a theoretically-dense part (3.175 g/cm3, according to rule of mixtures). These parts exhibited higher density and finer microstructure than a commercially-available sintered SiC from Saint-Gobain (Hexoloy Enhanced, 3.153 g/cm3 and d50 = 4.837 µm). Due to the optimized microstructure, Verco SiC parts exhibited the highest Vickers (2628.30 ± 44.13 kg/mm2) and Knoop (2098.50 ± 24.8 kg/mm2) hardness values of any SiC ceramic, and values equal to those of the "gold standard" hot-pressed boron carbide (PAD-B4C). While the fracture toughness of hot-pressed SiC materials (~4.5 MPa m1/2) are almost double that of Verco SiC (2.4 MPa m1/2), Verco SiC is a better performing ballistic product, implying that the higher hardness of the theoretically-dense, clean-grain boundary, fine-grained SiC is the defining mechanical property for optimization of ballistic behavior.

Graphene, a sheet of carbon atoms organized in a honeycomb lattice, is a two dimensional crystal. Even though the material has been known for a long time, only recently has it stimulated considerable interest across different research areas. Graphene is interesting not only as a platform to study fundamental physics in two dimensions, but it also has great potential for post-silicon microelectronics owing to its exceptional electronic properties. Of the several methods known to produce graphene, epitaxial growth of graphene by sublimation of silicon carbide is probably the most promising for practical applications. This thesis is a theoretical study of the growth kinetics of epitaxial graphene on SiC(0001). We propose a step-flow growth model using coarse-grained kinetic Monte Carlo (KMC) simulations and mean-field rate equations to study graphene growth on both vicinal and nano-faceted SiC surfaces. Our models are consistent with experimental observations and provide quantitative results which will allow experimenters to interpret the growth morphology and extract energy barriers from experiments. Recently, it has been shown that graphene grown epitaxially on metal surfaces may lead to potential applications such as large area transparent electrodes. To study deposition-type epitaxial growth, we investigate a new theoretical approach to this problem called the phase field method. Compared to other methods this method could be less computationally intensive, and easier to implement at large spatial scales for complicated epitaxial growth situations.

The need for post-CMOS nanoelectronics has led to the investigation of innovative device structures and materials. Graphene, a zero bandgap semiconductor with ballistic transport properties, has great potential to extend diversification and miniaturization beyond the limits of CMOS. The goal of this work is to study the growth of graphene on SiC using the novel method of selective graphitization. The major contributions of this research are as follows - First, epitaxial graphene is successfully grown on selected regions of SiC not capped by AlN deposited by molecular beam epitaxy. This contribution enables the formation of electronic-grade graphene in desired patterns without having to etch the graphene or expose it to any detrimental contact with external chemicals. Etching of AlN opens up windows to the SiC in desirable patterns for subsequent graphitization without leaving etch-residues (determined by XPS). Second, the impact of process parameters on the growth of graphene is investigated. Temperature, time, and argon pressure are the primary growth-conditions altered. A temperature of 1400oC in 1 mbar argon for 20 min produced the most optimal graphene growth without significant damage to the AlN capping-layer. Third, first-ever electronic transport measurements are achieved on the selective epitaxial graphene. Hall mobility of about 1550 cm2/Vs has been obtained to date. Finally, the critical limitations of the selective epitaxial graphene growth are enumerated. The advent of enhanced processing techniques that will overcome these limitations will create a multitude of opportunities for applications for graphene grown in this manner. It is envisaged to be a viable approach to fabrication of radio-frequency field-effect transistors.

<p>As a power device material, SiC has gained remarkable attention to its high thermal conductivity and high breakdown electric field. SiC bipolar junction transistors (BJTs) are interesting for applications as power switch for 600 V-1200 V applications. The SiC BJT has potential for very low specific on-resistances and this together with high temperature operation makes it very suitable for applications with high power densities. One disadvantage of the BJT compared with MOSFETs and Insulated Gate Bipolar Transistors (IGBTs) is that the BJT requires a more complex drive circuit with higher power capability. For the SiC BJT to become competitive with field effect transistors, it is important to achieve high current gains to reduce the power required by the drive circuit. Although much progress in SiC BJTs has been made, SiC BJTs still have low common emitter current gain typically in the range 10-50. In this work, a record high current gain exceeding 60 has been demonstrated for a SiC BJT with a breakdown voltage of 1100 V. This result is attributed to an optimized device design, a stable device process and state-of-the-art epitaxial base and emitter layers.</p><p>A new technique to fabricate the extrinsic base using epitaxial regrowth of the extrinsic base layer was proposed. This technique allows fabrication of the highly doped region of the extrinsic base a few hundred nanometers from the intrinsic region. An important factor that made removal of the regrowth difficult was that epitaxial growth of very highly doped layers has a faster lateral than vertical growth rate and the thickness of the p+ layer therefore has a maximum close to the base-emitter sidewall. A remaining p+ regrowth spacer at the edge of the base-emitter junction is proposed to explain the low current gain.</p><p>Under high power operation, the SiC BJTs were strongly influenced by self-heating, which significantly limits the performance of device. The DC I-V characteristics of 4H-SiC BJTs have also been studied in the temperature range 25 °C to 300 °C. The DC current gain at 300 °C decreased 56 % compared to its value at 25 °C. Selfheating effects were quantified by extracting the junction temperature from DC measurements.</p><p>To form good ohmic contacts to both n-type and p-type SiC using the same metal is one important challenge for simplifying SiC Bipolar Junction Transistor (BJT) fabrication. Ohmic contact formation in the SiC BJT process was investigated using sputter deposition of titanium tungsten to both n-type and p-type followed by annealing at 950 oC. The contacts were characterized with linear transmission line method (LTLM) structures. The n+ emitter structure and the p+ base structure contact resistivity after 30 min annealing was 1.4 x 10-4 Ωcm2 and 3.7 x 10-4 Ωcm2, respectively. Results from high-resolution transmission electron microscopy (HRTEM), suggest that diffusion of Si and C atoms into the TiW layer and a reaction at the interface forming (Ti,W)C1-x are key factors for formation of ohmic contacts.</p>