This thesis details work undertaken over the past three and a half years looking at the optical properties of silicon-on-insulator waveguide arrays and 1D photonic crystal microcavities. Chapter 1 contains relevant background information, while chapters 2, 3 and 4 contain results of experimental work. Chapter 5 summarises the results and conclusions of the preceding chapters and also suggests some directions for possible future research. Chapter 1 starts by introducing some of the fundamental aspects of guided wave optics and how these relate to silicon-on-insulator waveguides. The modes of single,uncoupled silicon waveguides are described, along with a brief description of how such waveguides can be fabricated. Following this a short introduction to optical cavities and the relevant parameters that can be used to describe them is provided. In Chapter 2 results are presented that experimentally confirm the presence of couplinginduced dispersion in an array consisting of two strongly-coupled silicon-on-insulator waveguides. This provides an additional mechanism to tailor dispersion and shows that it is possible to achieve anomalous dispersion at wavelengths where the dispersion of a single wire would be normal. In Chapter 3 the focus switches to the linear properties of 1D photonic crystal microcavities in silicon. The optical transmission of a number of different devices are examined allowing the identification of suitable microcavities for use in nonlinear measurements. Microcavities with Q-factors in excess of ∼40,000 were selected for use in the work presented in Chapter 4, whilst the possibility of thermally tuning the microcavity resonances is also investigated. A cavity resonance shift of 0.0770± 0.0004 nm K-1 is measured experimentally. Chapter 4 looks at the nonlinear transmission of those microcavities identified as suitable in Chapter 3. More specifically, the response of the microcavities to thermal and free carrier induced bistability is considered. Thermally induced bistability is observed at a threshold power of 240 μW for the particular cavity chosen, with a thermal time of 0.6 μs also measured. Free carrier induced bistability is then observed for pulses with nanosecond durations and milliwatt peak powers. Following that, the interplay of thermal and free carrier effects is observed using input pulses of a suitable duration.

Lau Wai Kwok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references. / Acknowledgement --- p.iv / Abstract --- p.v / Chapter Chapter 1 --- Introduction --- p.1-1 / Chapter 1.1 --- Perspective --- p.1-1 / Chapter 1.2 --- MEDICI - The Simulation Package --- p.1 -2 / Chapter 1.3 --- Overview --- p.1-3 / Chapter Chapter 2 --- The Emergence of SOI Devices --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Advantages of SOI Devices --- p.2-1 / Chapter 2.2.1 --- Reliability Improvement --- p.2-2 / Chapter 2.2.2 --- Total Isolation --- p.2-3 / Chapter 2.2.3 --- Improved Junction Structure --- p.2-4 / Chapter 2.2.4 --- Integrated Device Structure --- p.2-5 / Chapter 2.3 --- Categories of SOI Devices --- p.2-6 / Chapter 2.3.1 --- Thick Film SOI Devices --- p.2-7 / Chapter 2.3.2 --- Thin Film SOI Devices --- p.2-8 / Chapter 2.3.3 --- Medium Film SOI Devices --- p.2-8 / Chapter 2.4 --- Drawbacks of SOI Devices --- p.2-9 / Chapter 2.4.1 --- Floating Body Effects --- p.2-9 / Chapter 2.4.2 --- Parasitic Bipolar Effects --- p.2-11 / Chapter 2.4.3 --- Cost --- p.2-15 / Chapter 2.5 --- Manufacturing Methods --- p.2-16 / Chapter 2.5.1 --- Epitaxy-Based Method --- p.2-16 / Chapter 2.5.2 --- Recrystallization-Based Method --- p.2-18 / Chapter 2.5.3 --- Wafer Bonding Based Method --- p.2-19 / Chapter 2.5.4 --- Oxidation Based Method --- p.2-20 / Chapter 2.5.5 --- Implantation Based Method --- p.2-22 / Chapter 2.6 --- Future Trend --- p.2-22 / Chapter 2.7 --- The Quest for Silicon-On-Nitride Structure --- p.2-23 / Chapter Chapter 3 --- Description of Body-Contact SOI Structure --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Current Status of Body-Contact SOI Structure --- p.3-1 / Chapter 3.3 --- The Body-Contact SOI Structure to be studied --- p.3-4 / Chapter 3.4 --- Impact on Device Fabrication --- p.3-7 / Chapter 3.4.1 --- Fabrication of Conventional Bulk CMOS --- p.3-7 / Chapter 3.4.2 --- Fabrication of Conventional SOI CMOS --- p.3-8 / Chapter 3.4.3 --- Fabrication of BC SOI CMOS --- p.3-10 / Chapter Chapter 4 --- Device Simulations --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- MEDICI --- p.4-1 / Chapter 4.2.1 --- Basic Equations --- p.4-2 / Chapter 4.2.2 --- Solution Methods --- p.4-3 / Chapter 4.2.3 --- Initial Guess --- p.4-6 / Chapter 4.2.4 --- Grid Allocations --- p.4-7 / Chapter 4.2.5 --- Source File --- p.4-8 / Chapter 4.3 --- Structures for Simulations --- p.4-9 / Chapter 4.3.1 --- l.2μm NMOS Bulk (LDD) --- p.4-9 / Chapter 4.3.2 --- 1.2μm SOI(O) NMOS 1000/3500 NBC --- p.4-11 / Chapter 4.3.3 --- 1.2μm SOI(N) NMOS 1000/3500 NBC --- p.4-12 / Chapter 4.3.4 --- 1.2μm SOI(O) NMOS 1000/3500 WBC --- p.4-13 / Chapter 4.3.5 --- 1.2μm SOI(N) NMOS 1000/3500 WBC --- p.4-14 / Chapter 4.4 --- Summary --- p.4-14 / Chapter Chapter 5 --- Simulation Results --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Comparisons of Different Structures --- p.5-1 / Chapter 5.2.1 --- Impurity Profiles of Structures --- p.5-2 / Chapter 5.2.2 --- Body Effect --- p.5-10 / Chapter 5.2.3 --- Breakdown Voltage and Transistor Current Driving --- p.5-16 / Chapter 5.2.4 --- Transconductance and Mobility --- p.5-20 / Chapter 5.2.5 --- Subthreshold Swing --- p.5-23 / Chapter 5.3 --- Dependence on Key Structure Parameters --- p.5-29 / Chapter 5.3.1 --- Dependence on Insulator Thickness --- p.5-29 / Chapter 5.3.2 --- Dependence on Silicon Overlayer Thickness --- p.5-34 / Chapter 5.3.3 --- Dependence on Size of Body-Contact --- p.5-37 / Chapter 5.4 --- Summary --- p.5-40 / Chapter Chapter 6 --- Reduction of Latch-up Susceptibility --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Construction of a p-channel MOS Transistor --- p.6-2 / Chapter 6.2.1 --- Threshold Voltage and Body Effect --- p.6-3 / Chapter 6.2.2 --- I-V Characteristics --- p.6-3 / Chapter 6.2.3 --- Transconductance --- p.6-5 / Chapter 6.2.4 --- Subthreshold Swing --- p.6-5 / Chapter 6.3 --- Mechanism of Latch-up in CMOS --- p.6-6 / Chapter 6.4 --- Construction of a CMOS Invertor for Simulation --- p.6-10 / Chapter 6.5 --- Latch-up Susceptibility Dependence --- p.6-16 / Chapter 6.5.1 --- Dependence on Insulator Thickness --- p.6-16 / Chapter 6.5.2 --- Dependence on N-well Depth --- p.6-19 / Chapter 6.5.3 --- Dependence on Transistor Separation --- p.6-22 / Chapter 6.5.4 --- Dependence on Size of Body-Contact --- p.6-25 / Chapter 6.6 --- Summary --- p.6-28 / Chapter Chapter 7 --- Conclusions --- p.7-1 / Chapter 7.1 --- Summary --- p.7-1 / Chapter 7.2 --- Recommendation --- p.7-3 / Reference / Appendix A

Thesis (Ph.D.)--McMaster University, 2006. / Supervisor: P.E. Jessop Includes bibliographical references ( leaves 166-179).

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.

For the high performance integrated circuits applications such as microprocessors, memories and high power devices, the metal-oxide-semiconductor field effect transistors (MOSFETs) is the most important device due to its low cost, power consumption and scalable property especially. However, the aggressive scaling of conventional MOS devices suffered from noticeable short channel effects such as drain induction barrier lower, punch through, and direct tunneling gate leakage. Those problems not only lower the gate control ability but also increase the standby power consumption. For future VLSI devises below 65 nm regimes, silicon-on-insulator (SOI) and high-k/metal gate MOSFETs are considered to be possible candidates because of faster operation speed and lower power consumption. Therefore, this dissertation investigates the electrical characteristics and reliability issues of novel MOSFETs for 65 nm and below technology. It is roughly divided into two parts, partially depleted (PD) SOI MOSFETs and high-k/metal gate stack MOSFETs, respectively. In the first part, we systematically investigate the mechanism of gate-induced floating body effect (GIFBE) for advanced PD SOI n-MOSFETs. Based on different operation conditions, it was found that the dominant mechanism can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron-valence band (EVB) tunneling. Analyzing the GIFBE in different temperature provides further evidence that the accumulation of holes in the body results from the AHI induced direct tunneling current from the poly-Si gate. In addition, we proposed an approach by bending silicon substrate to further study the impact of mechanical strain on GIFBE. The experimental result indicates that the strain effect indeed decreases the gate leakage current, but increases the hole-valence band (HVB) tunneling current, which indicates that GIFBE becomes serious under mechanical strain. Based on our proposed AHI model, this phenomenon can be mainly due to strain-induced band gap narrowing in the poly-Si gate. In p-type MOSFETs, the reliability issue, named negative bias temperature instability (NBTI), is the dominant degradation mechanism during ON-state operation. Therefore, we also investigate the GIFBE on NBTI degradation for PD SOI p-MOSFETs. The experimental results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ poly gate. However, based on different operation conditions, we found the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. Therefore, we propose the anode electron injection (AEI) model, similar to anode hole injection model, to explain how this main electron origin is generated during the NBTI stress. Finally, based on our proposed model, we further study influence of mechanical strain on GIFBE for SOI p-MOSFETs. On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 45 nm technology node due to unacceptable gate leakage current. Therefore, in the second part of this thesis, we investigate the electrical characteristics and physical mechanisms for MOSFETs with HfO2/TixN1-x stacks by using split C-V, DC Id-Vg, and charge pumping techniques. The experimental results indicates that different ratio of Ti strongly affect various parameters, including threshold voltage, mobility, and subthreshold swing, respectively. In addition, the gate leakage current is also strongly dependent on the nitrogen in metal gate. By charge pumping technique, it was found that with increasing Ti concentration of metal gate, there is a trade-off relationship among the interface traps and bulk defects of high-k dielectric. This phenomenon is associated with the amount of nitride diffusion from the metal gate to high-k bulk and SiO2/Si interface layer. In the aspects of reliability, charge trapping in high-k gate stacks remains an important issue since it causes the threshold voltage (Vth) shift and drive current degradation. This phenomenon can be attributed to a large number of pre-existing traps in the high-k dielectric layer. In real circuit operation, the devices are generally operated in the dynamic condition. Therefore, the following study further investigates Vth instability of Hf-based n-MOSFETs under the dynamic bias operation. The static condition was also performed on the identical device for a comparison. The results indicate threshold voltage (Vth) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. In addition, the Vth shift clearly increases with an increase in dynamic stress operation frequency. According to these experimental results, we propose a possible physical model for electron trapping phenomena under dynamic stress. Based on our proposed model, we further dynamic stress induced charge trapping characteristics for devices with different Ti1-xNx composition of metal-gate electrodes. In addition, we further respectively investigates the temperature dependence of dynamic positive bias stress (PBS) and negative bias stress (NBS) degradation in n-type and p-type MOSFETs with high-k/metal gate stacks. The experimental results indicate there is a contrary trend in temperature dependence of Vth shifts for n- and p-MOSFETs under dynamic PBS and NBS, respectively. The Vth shift decreases with increasing temperature for n-MOSFETs under dynamic PBS. This is due to the thermal emission of trapped electrons in high temperature, leading to the reduction in. A contrary trend with temperature for p-MOSFETs under dynamic NBS can be attributed to the interface trap generation induced by NBTI. On the other hand, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability concern in device scaling. However, the stress-induced drain leakage current degradation in device with high-k/metal gate stacks has not received as much attention. In fact, the GIDL behavior is associated with phenomenon of charge trapping in high-k dielectric layer. Therefore, the final study is to investigate the effects of channel hot carrier stress (CHCS) on the gate-induced drain leakage current (GIDL) for n-MOSFETs with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the IGIDL after CHCS, and observed that the magnitude of IGIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric.

Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaves 116-117).

Couplers that can couple light vertically between stacked waveguides are finding importance in the push towards higher density and lower cost optoelectronics. A compact grating coupler (12.8mum) designed by a former student is implemented in this project. The device is patterned by reactive-ion-etch into silicon-on-insulator with a 250 nm thick device layer, ensuring single mode operation. Alignment marks are patterned into the backside so that aligned bonding can be carried out. A die bonding recipe is developed using an intermediate adhesive film of SU-8-2. A novel approach to creating optically smooth input facets is included in the final steps of the process. Optical testing remains to be done.

Thesis (M.S.)--Oregon State University, 2005. / Printout. Includes bibliographical references (leaves 53-54). Also available on the World Wide Web.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--Rochester Institute of Technology, 2005. / Typescript. Includes bibliographical references (leaves 40-41).