Thesis (PhD)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: In order to facilitate the creation of complex and robust RSFQ digital logic circuits an extensive library of electronic design automation (EDA) tools is a necessity. It is the aim of this work to introduce various methods to improve the current state of EDA in RSFQ circuit design. Firstly, Monte Carlo methods such as Latin Hypercube sampling and Sobol sequences are applied for their variance reduction abilities in approximating circuit yield. In addition, artificial neural networks are also investigated for their applicability in modeling the parameter-yield space. Secondly, a novel technique for circuit functional testing using automated state machine extraction is presented, which greatly simplifies the logical verification of a circuit. This method is also used, along with critical timing extraction, to automatically generate Hardware Description Language(HDL) models which can be used for high level circuit design. Lastly, the Greedy Local search, Simulated Annealing and Genetic Algorithm meta-heuristics were statistically compared in a novel manner using a yield model provided by artificial neural networks. This is done to ascertain their performance in optimising RSFQ circuits in relation to yield. The variance reduction techniques of Latin Hypercube Sampling and Sobol sequences were shown to be beneficial for the use with RSFQ circuits. For optimisation purposes the use of Simulated Annealing and Genetic Algorithms were shown to improve circuit optimisation for possible multi-modal search spaces. An HDL model is also successfully generated from a complex RSFQ circuit for use in high level circuit design which includes critical timing and propagation latency. All the techniques presented in this study form part of a software library that can be further refined and extended in future work.

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells. / AFRIKAANSE OPSOMMING: "Rapid Single Flux Quantum" (RSFQ) selle is van sleutelbelang in die ontwerp van komplekse en toepaslike RSFQ elektroniese stroombane. Hierdie selle is laevlak stroombaanelemente wat herhaaldelik gebruik word om groter RSFQ bane mee te bou. Versigtige ontwikkeling is nodig om hierdie selle eenvoudig vir uitleg en vervaardiging te hou terwyl dit ook betroubaar is vir wye gebruik. Selfunksionaliteit word geverifieer deur middel van simulasies, waarna selle vir vervaardiging uitgelê word in spesiale sagtewarepakette. Induktansie van supergeleierstrukture op vervaardigde skyfies word deur versigtige modellering met behulp van numeriese veldoplossingsagteware onttrek. In hierdie tesis is ’n selbiblioteek ontwerp deur bestaande (gepubliseerde) selle verder te analiseer en optimeer, en deur nuwe selle te ontwerp om die biblioteek volledig te maak. Selle wat aangepas is vir hierdie biblioteek sluit die Josephson-Transmissielyn (JTL), Verdeler, Samevoeger, DWipkring (DFF), T-Wipkring (TFF), NIE, EN, OF en XOF, asook die DC-SFQ en SFQ-DC selle en Passiewe Transmissielyn (PTL) drywers en ontvangers in. Nuwe selle sluit die NOF, NEN en XNOF hekke in. Die selle is ontwerp en uitgelˆe vir beide IPHT se RSFQ1D 1kA/cmª en Hypres se4.5kA/cmª prosesse. Die selle in die biblioteek toon goeie voorspanningstroom-werksmarges, soos verkry deur simulasie (> ±26%). Parameters en berekende induktansies vir alle selle word in die tesis gelys vir naslaandoeleindes. Vir die daarstel van ’n volledige en geverifieerde RSFQ selbiblioteek is selontwerpe vir vervaardiging na IPHT en Hypres gestuur. Aangesien vervaardiging slegs een maal per jaar by IPHT gedoen word, is die skyfies egter nog nie beskikbaar nie. Na vervaardiging kan die skyfies egter getoets word om selfunksionaliteit in die laboratorium te meet. Ten einde hierdie toetsing vir enige medewerker te vergemaklik, word alle toetsparameters soos voorspanningstroom en intreeseinpatrone in die tesis gedefinieer.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: Thorough layout verification of superconductor integrated circuits goes beyond design rule checking and parameter value extraction. The former is used to verify adherence to process design rules, and the latter to determine the element values of components such as inductors and resistors and Josephson junction critical currents. Still, neither gives much warning against subtle layout errors that could result in unintended parasitic elements, or a circuit that does not reflect the original circuit topology. A specialized implementation for Cadence Virtuoso allows layout-versus-schematic verification, but it is limited both to commercial software and in terms of its usefulness. Parameter extraction software such as InductEx is used to extract the component element values of a circuit from its layout if the circuit topology is provided as a netlist, which is mostly created by the designer. However, the element values are extracted for the supplied topology, even if a layout mistake such as creating a connection to the wrong node or a mistake in the netlist results in a model mismatch. After a failed verification, further diagnosis is required to determine whether the error is indeed in the layout or in the input topology - prolonging the verification process significantly. Here we present a free-standing layout-versus-schematic verification toolkit for superconductive integrated circuits, and discuss its implementation after systematically considering the algorithms at its core. We demonstrate results of the layout-versus-schematic verification and how the layout-versus-schematic toolkit is used as a whole in conjunction with InductEx to perform automated parameter extraction for cell-level layout verification. The current version of this toolkit provides the user with three stand-alone tools that are best used in conjunction with InductEx: A GDSII file flattener, a layout-to-schematic netlist extractor (with the option of viewing a pictorial reconstruction of the netlist and schematic) and a netlist comparison tool by which the user can determine whether a layout agrees with an input schematic. We conclude that the netlist comparison and viewing tool provides a valuable method for expediting the layout verification process, making it more efficient and minimizing the chances of mistakes. In its current form the layout-to schematic tool is still limited in that it cannot yet fully support circuits with mutual coupling. Although many improvements can still be made to this toolkit, the implemented version of these tools can already provide great benefit to Rapid Single Flux quantum (RSFQ) cell designers. / AFRIKAANSE OPSOMMING: Deeglike uitleg verifikasie van supergeleier geïntegreerde stroombane strek verder as bloot die nasien van ontwerpreëls en die onttrekking van parameter waardes. Eersgenoemde word gebruik om vas te stel of daar voldoen word aan die proses se ontwerpreëls, en laasgenoemde om die waardes van komponente soos induktors en resistors en die kritiese strome van Josephson aansluitings te bepaal. Nogtans bied nie een van hulle veel waarskuwing teen subtiele uitlegfoute wat onbeplande parasitiese elemente kan veroorsaak nie, of teen ‘n stroombaan wat nie die oorspronklike stroombaan topologie weerspieël nie. ‘n Gespesialiseerde implementasie van Cadence Virtuoso maak LVS (layout-versus-schematic) verifikasie moontlik, maar dit is beperk tot kommersiële sagteware en ook beperk in terme van bruikbaarheid. Parameter onttrekking sagteware soos InductEx word gebruik om waardes van die komponent-elemente van ‘n stroombaan vanuit die uitleg te onttrek wanneeer die stroombaan topologie as ‘n netlist, wat meestal deur die ontwerper geskep is, voorsien word. Die elementwaardes word egter onttrek volgens die topologie wat verskaf is, al is daar uitlegfoute, soos byvoorbeeld wanneer ‘n koppeling met ‘n verkeerde node plaasvind, of wanneer daar netlist foute is wat modelteenstrydighede veroorsaak. Na ‘n mislukte verifikasie poging word verdere diagnostiese stappe gedoen om te bepaal of die fout in die uitleg lê, of in die spesifieke topologie wat verskaf is, wat natuurlik die verifikasieproses aansienlik verleng. Hier stel ons ‘n vrystaande LVS verifikasie sagteware-pakket vir supergeleier geïntegreerde stroombane bekend, en bespreek, deur middel van die algoritmes wat die kern daarvan uitmaak, die implementering van hierdie sagteware-toestel. Ons bied die resultate van die LVS verifikasie aan en wys hoe die LVS sagteware toestel as geheel saam met InductEx gebruik kan word om automatiese parameter uittrekking vir sel-vlak uitleg verifikasie te berwerkstellig. Die huidige weergawe van die pakket bied die verbruiker drie alleenstaande programme wat verkieslik saam met InductEx gebruik moet word: ‘n GDSII “file flattener”, ‘n uitleg-tot-schematiese diagram netlist ekstraktor (met die opsie om ‘n herkonstruktueerde beeld van netlist en skematiese diagram te besigtig) en ‘n netlist vergelyking toestel waarmee die verbruiker kan vasstel of ‘n uitleg met ‘n oorspronklike skematiese diagram ooreenstem. Ons lei af dat die netlist vergelyking toestel ‘n waardevolle metode bied om die uitleg verifikasie proses te bespoedig en vergemaklik en die kanse van foute te minimaliseer. In sy huidige vorm is die uitleg-tot-skematiese diagram toestel beperk omdat dit nog nie stroombane met koppeling kan steun nie.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第20033号 / 情博第628号 / 新制||情||109(附属図書館) / 33129 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 髙木 直史, 教授 小野寺 秀俊, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Thesis (MScEng)--University of Stellenbosch, 2001. / ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) logic cells are discussed, and new cells developed. The expected yield of every cell is computed through a Monte Carlo analysis, and where necessary these cells are optimized for use in a complex system. A mathematical study of the Josephson junction and SQUIDs (Superconducting Quantum Interference devices) as switching elements precede a discussion on the operation of RSFQ and COSL (Complementary Output Switching Logic.) These logic families are implemented in low temperature niobium technology, and require liquid helium cooling. A 10 GHz oversampling delta modulating analogue-to-digital converter is then designed and constructed using RSFQ and COSL building blocks in a hybrid configuration. The design emphasis is on devising ways to test the operation of RSFQ with limited equipment. Yield analysis procedures on the complex system are discussed, followed by a detailed discussion on the circuit layout and layout problems. Software routines are developed to calculate the required dimensions of layout structures. / AFRIKAANSE OPSOMMING: Rapid Single Flux Quantum (RSFQ) logiese selle word bespreek, en enkele nuwe selle word ontwikkel. Die verwagte opbrengs, of kans dat 'n sel sal werk, word bereken deur 'n Monte Carlo analise. Waar nodig word selle met behulp van die analise verbeter vir gebruik in 'n komplekse stelsel. 'n Wiskundige studie van die Josephson-vlak en SQUIDs (Superconducting Quantum Interference devices) word gevolg deur 'n bespreking oor die werking van RSFQ en COSL (Complementary Output Switching Logic.) Hierdie logiese families word geïmplementeer in laetemperatuur niobiumtegnologie, en vereis vloeibare helium-verkoeling. 'n Deltamodulerende analoog-na-digitale omsetter met 'n intree-monstertempo van 10 GHz word ontwerp en vervaardig met 'n hibriede samestelling van RSFQ en COSL boublokke. Die ontwerp fokus op maniere om die werking van RSFQ teen 10 GHz te kan toets met die beperkte toerusting wat beskikbaar is. Opbrengsanalise op die komplekse stelsel word bespreek, gevolg deur 'n volledige bespreking van die stroombaanuitlegprosedure en uitlegprobleme. Roetines word in sagteware ontwikkel om die nodige dimensies van uitlegstrukture te bereken.

L'objectif de ce travail était d’élaborer la brique de base d'un convertisseur analogique numérique supraconducteur à architecture pipeline, fonctionnant à 30GHz de fréquence d’échantillonnage. Ce convertisseur est constitué d’un bloc de N comparateurs disposés en cascade le long d’une ligne de transmission. Chaque étage de comparaison est constitué d'un SQUID rf mutuellement couplé à un tronçon de ligne de transmission. Lorsque le signal à convertir arrive à la hauteur d'un comparateur, il génère un champ magnétique qui induit un courant dans le SQUID rf. Ce courant pourra faire commuter la jonction Josephson du SQUID rf dans certains cas, en fonction des caractéristiques internes de la jonction Josephson du SQUID et de son environnement. La commutation, qui s’accompagne de l’apparition d’une impulsion de tension quantifiée SFQ, a été étudiée de manière théorique et expérimentale en fonction des différents paramètres du problème. / Superconductive analogue to digital converters (ADC) generally have speed and power dissipation advantages which should enable their application in telecommunication, medicine, and where an analogue signal (delivered e.g. by a sensor) needs to be digitized for post-processing.We are developing a new concept of analogue to digital converter using high critical temperature (Tc=90K) superconductors and operating at 30GHz; this converter is based an original structure, the pipeline architecture. The principle is to place a cascade of N comparators along a transmission line on which propagates the up-converted analogue signal. The carrier frequency is used in this case as a sampling signal.Each comparator, made with a SQUID loop, produces one bit at the carrier frequency: it codes the input signal by generating or not an RSFQ pulse (respectively "1” or “0"), and passes the residue (attenuated signal) in the following comparator.Here, we present steps for the comparator optimisation and mask design.Besides simulation results, we present the measurements at 30GHz carrier frequency of the comparator designed at low critical temperature (LTS). Finally, we suggest other tools to develop the optimised low critical temperature converter and we proposed the concept of the comparator operating at high critical temperature (HTS).