Este trabalho trata do espaço da cozinha dentro das unidades habitacionais de baixa renda. Compara as cozinhas das habitações espontâneas - construídas pelo próprio morador - com as projetadas por profissionais e oferecidas pelo sistema de governo. O estudo de caso foi feito no Dique da Vila Gilda, em Santos-SP. Foram analisadas as áreas das cozinhas em relação ao valor total da unidade e as atividades nelas desenvolvidas. Foram pesquisadas também as alterações feitas pelos moradores em unidades planejadas, no sentido de melhor adaptá-las ao seu uso. Os resultados desta pesquisa contribuem para elevar a qualidade da produção habitacional visando sempre a satisfação do usuário. / This work treats of the kitchen space within the low-income housing units. It compares the kitchens of spontaneous dwellings-built by the dweller - with the designed by professional and offered by system of Government. The case study was done at Dique da Vila Gilda, in Santos-SP. The kitchen areas were analysed in relation to the total value of the unit and the activities carried out in them. Changes made by residents in planned units were also surveyed in order to better adapt them to their use. The results of this research will contribute to raising the quality of housing production aiming always user satisfaction.

Este trabalho trata do espaço da cozinha dentro das unidades habitacionais de baixa renda. Compara as cozinhas das habitações espontâneas - construídas pelo próprio morador - com as projetadas por profissionais e oferecidas pelo sistema de governo. O estudo de caso foi feito no Dique da Vila Gilda, em Santos-SP. Foram analisadas as áreas das cozinhas em relação ao valor total da unidade e as atividades nelas desenvolvidas. Foram pesquisadas também as alterações feitas pelos moradores em unidades planejadas, no sentido de melhor adaptá-las ao seu uso. Os resultados desta pesquisa contribuem para elevar a qualidade da produção habitacional visando sempre a satisfação do usuário. / This work treats of the kitchen space within the low-income housing units. It compares the kitchens of spontaneous dwellings-built by the dweller - with the designed by professional and offered by system of Government. The case study was done at Dique da Vila Gilda, in Santos-SP. The kitchen areas were analysed in relation to the total value of the unit and the activities carried out in them. Changes made by residents in planned units were also surveyed in order to better adapt them to their use. The results of this research will contribute to raising the quality of housing production aiming always user satisfaction.

This thesis deals with the topic of money management and various methods of its use in trading on the stock markets. The work tries to show the important role played by money management and how such discipline can fundamentally change the behavior of business systems. There is also pointed out the importance of reconciling money management and psychological factors of a trader. In the practical part, I work with real data from the Commodity Exchange and by using Monte Carlo analysis I simulate how a suitable money management can gigantically affect the overall system performance.

No description available.

No description available.

The scaling of VLSI technology has spurred a rapid growth in the semiconductor industry. With the CMOS device dimension scaling to and beyond 90nm technology, it is possible to achieve higher performance and to pack more complex functionalities on a single chip. However, the scaling trend has introduced drastic variation of process and design parameters, leading to severe variability of chip performance in nanometer regime. Also, the manufacturing community projects CMOS will scale for three to four more generations. Since the uncertainties due to variations are expected to increase in each generation, it will significantly impact the performance of design and consequently the yield. Another challenging issue in the nanometer IC design is the high power consumption due to the greater packing density, higher frequency of operation and excessive leakage power. Moreover, the circuits are usually over-designed to compensate for uncertainties due to variations. The over-designed circuits not only make timing closure difficult but also cause excessive power consumption. For portable electronics, excessive power consumption may reduce battery life; for non-portable systems it may impose great difficulties in cooling and packaging. The objective of my research has been to develop design methodologies to address variations and power dissipation for reliable circuit operation. The proposed work has been divided into three parts: the first part addresses the issues related with power/ground noise induced by clock distribution network and proposes techniques to reduce power/ground noise considering the effects of process variations. The second part proposes an elastic pipeline scheme for random circuits with feedback loops. The proposed scheme provides a low-power solution that has the same variation tolerance as the conventional approaches. The third section deals with discrete buffer and wire sizing for link-based non-tree clock network, which is an energy efficient structure for skew tolerance to variations. For the power/ground noise problem, our approach could reduce the peak current and the delay variations by 50% and 51% respectively. Compared to conventional approach, the elastic timing scheme reduces power dissipation by 20% − 27%. The sizing method achieves clock skew reduction of 45% with a small increase in power dissipation.

Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution under continuous solution space. However, it is more complex to use Lagrangian relaxation under discrete solution space. The Lagrangian dual problem is non-convex and previously a sub-gradient method was used to solve it. The sub-gradient method is a greedy approach for substituting gradient method in the deepest descent method, and has room for further improvement. In addition, Lagrangian sub-problem cannot be solved directly by mathematical approaches under discrete solution space. Here we propose a new Lagrangian relaxation-based method for simultaneous gate sizing and Vt assignment under discrete solution space. In this work, some new approaches are provided to solve the Lagrangian dual problem considering not only slack but also the relationship between Lagrangian multipliers and circuit timing. We want to solve the Lagrangian dual problem more precisely than did previous methods, such as the sub-gradient method. In addition, a table-lookup method is provided to replace mathematical approaches for solving the Lagrangian sub-problem under discrete size and Vt options. The experimental results show that our method can lead to about 50 percent and 58 percent power reduction subject to the same timing constraints compared with a Lagrangian relaxation method using sub-gradient method and a state-of-the-art previous work. These two methods are implemented by us for comparison. Our method also results in better circuit timing subject to tight timing constraints.

For any congestion control mechanisms, the most fundamental design objectives are stability and scalability. However, achieving both properties are very challenging in such a heterogeneous environment as the Internet. From the end-users' perspective, heterogeneity is due to the fact that different flows have different routing paths and therefore different communication delays, which can significantly affect stability of the entire system. In this work, we successfully address this problem by first proving a sufficient and necessary condition for a system to be stable under arbitrary delay. Utilizing this result, we design a series of practical congestion control protocols (MKC and JetMax) that achieve stability regardless of delay as well as many additional appealing properties. From the routers' perspective, the system is heterogeneous because the incoming traffic is a mixture of short- and long-lived, TCP and non-TCP flows. This imposes a severe challenge on traditional buffer sizing mechanisms, which are derived using the simplistic model of a single or multiple synchronized long-lived TCP flows. To overcome this problem, we take a control-theoretic approach and design a new intelligent buffer sizing scheme called Adaptive Buffer Sizing (ABS), which based on the current incoming traffic, dynamically sets the optimal buffer size under the target performance constraints. Our extensive simulation results demonstrate that ABS exhibits quick responses to changes of traffic load, scalability to a large number of incoming flows, and robustness to generic Internet traffic.

Thesis (Ph. D.)--Institute of Paper Chemistry, 1974. / Includes bibliographical references (leaves 140-146).

Thesis (Ph. D.)--Institute of Paper Chemistry, 1933.