This report deals with the design of a controller for SmartMedia™ flash memory cards, based on a hardware description found in the SmartMedia™ Interface Library - SMIL. The design was made on logic gate level, using standard cells in OrCAD Capture. After simulation of the design in PSpice A/D, it was exported as an EDIF netlist, which was used to make a chip layout in L-Edit, a layout tool for making integrated circuits. The layout was made using a method called Standard Place and Route - SPR, where the layout tool places standard cells from a library and connects them according to the EDIF netlist. A netlist which could be simulated in PSpice was extracted from the finished chip layout to verify that the function of the design was the same as before the transition from schematic to layout. The standard cells in the library used to make the chip layout have to meet certain criteria in order for both SPR and extraction to work and this is also discussed.

<p>This report deals with the design of a controller for SmartMedia™ flash memory cards, based on a hardware description found in the SmartMedia™ Interface Library - SMIL. </p><p>The design was made on logic gate level, using standard cells in OrCAD Capture. After simulation of the design in PSpice A/D, it was exported as an EDIF netlist, which was used to make a chip layout in L-Edit, a layout tool for making integrated circuits. The layout was made using a method called Standard Place and Route - SPR, where the layout tool places standard cells from a library and connects them according to the EDIF netlist. </p><p>A netlist which could be simulated in PSpice was extracted from the finished chip layout to verify that the function of the design was the same as before the transition from schematic to layout. </p><p>The standard cells in the library used to make the chip layout have to meet certain criteria in order for both SPR and extraction to work and this is also discussed.</p>