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The power supply designers choose flyback topology due to its promising features of design simplicity, cost effectiveness and multiple outputs handling capability. The designed product based on flyback topology should be smaller in size, cost effective and energy efficient. Similarly, designers focus on reducing the circuit losses while operating at high frequencies that affect the converter efficiency and performance. Based on the above circumstances, an energy efficient open loop high frequency flyback converter is designed and operated in MHz frequency region using step down multilayer PCB planar transformer. The maximum efficiency of 84.75% is observed and maximum output power level reached is 22.8W. To overcome the switching losses, quasi-resonant soft switching technique is adopted and a high voltage CoolMOS power transistor is used.

First measurements are made of the underlying event in calorimeter jet events at the LHC, using 37 pb-1 of pp collisions at √s = 7TeV, recorded during 2010 by the ATLAS detector. Results are compared for an assumed di-jet topology based on a single identified jet, and an exclusive di-jet requirement. The number of charged particles in the azimuthal region transverse to the jet axis is recorded, as well as their total and average transverse momentum. The total energy carried by all particles - charged and neutral - is also calculated, using the full calorimeter acceptance |η| < 4:8. Distributions are constructed to show the variation of these quantities versus the transverse momentum of the selected jet, over the range 20 - 800 GeV. Additional jets in the transverse region are shown to dramatically influence the measured activity. Software is developed to perform Bayesian iterative unfolding, testing closure of the process and stability with respect to the number of iterations performed. Pseudo-experiments are used to propagate systematic errors, and the intrinsic error due to unfolding is estimated. Although the correction relies on a prior probablitity distribution, model-dependence is reduced to an uncertainty comparable to or smaller than experimental systematic errors. The software is used to correct underlying event measurements for effects introduced by the ATLAS detector. Unfolded results are compared to predictions from different Monte Carlo event generators used in LHC analyses, showing general agreement in the range |η| < 2:5, but discrepancies in the forward region. Comparison with other ATLAS results shows compatible behaviour in events defined by any high-momentum charged particle, or by leptonic Z-boson decays.

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In the last twenty years, industrial and academic research has produced over one hundred new converter topologies for drives applications. Regrettably, most of the published work has been directed towards a single topology, giving an overall impression of a large number of unconnected, competing techniques. To provide insight into this wide ranging subject area, an overview of converter topologies is presented. Each topology is classified according to its mode of operation and a family tree is derived encompassing all converter types. Selected converters in each class are analysed, simulated and key operational characteristics identified. Issues associated with the practical implementation of analysed topologies are discussed in detail. Of all AC-AC conversion techniques, it is concluded that softswitching converter topologies offer the most attractive alternative to the standard hard switched converter in the power range up to 100kW because of their high performance to cost ratio. Of the softswitching converters, resonant dc-link topologies are shown to produce the poorest output performance although they offer the cheapest solution. Auxiliary pole commutated inverters, on the other hand, can achieve levels of performance approaching those of the hard switched topology while retaining the benefits of softswitching. It is concluded that the auxiliary commutated resonant pole inverter (ACPI) topology offers the greatest potential for exploitation in spite of its relatively high capital cost. Experimental results are presented for a 20kW hard switched inverter and an equivalent 20kW ACPI. In each case the converter controller is implanted using a digital signal processor. For the ACPI, a new control scheme, which eliminates the need for switch current and voltage sensors, is implemented. Results show that the ACPI produces lower overall losses when compared to its hardswitching counterpart. In addition, device voltage stress, output dv/dt and levels of high frequency output harmonics are all reduced. Finally, it is concluded that modularisation of the active devices, optimisation of semiconductor design and a reduction in the number of additional sensors through the use of novel control methods, such as those presented, will all play a part in the realisation of an economically viable system.

Conventional 'hard switching' converters suffer from significant switching loss due to the simultaneous imposition of high values of current and voltage on the devices during commutation. Resonant converters offer a solution to this problem. A review of resonant circuit topologies is presented, which includes a summary of the interference problems which may occur when using power converters in the rail traction environment. Particular attention is given to the Resonant DC Link Inverter (RDCLI) which shows a great deal of pronuse using currently available devices. The frequency domain simulation of RDCLIs is discussed as a means of rapidly evaluating circuit behaviour, especially in relation to modulation strategies. A novel modulation strategy is proposed for Resonant DC Link Inverters, based on a procedure known as Simulated Annealing which allows complex harmonic manipulations such as han-nonic minimisation, to be performed. This is despite the fact that RDCLIs are constrained to use Discrete Pulse Modulation whereby switch commutations are restricted to specific moments in time. The modulation algorithms were verified by use of a low-power test rig and the results obtained are compared against theoretical values. Details of the hardware implementation are also included. A single-phase pulse-converter input stage is described which may be incorporated into the Resonant DC Link Inverter topology. This input stage also benefits from soft-sVVItching and allows four-quadrant operation at any desired power factor. A modulation scheme based on SiMulated Annealing is proposed for the pulse-converter, to achieve hannomc control whilst also synchronising with the supply wavefon-n. Practical results are presented and compared with those obtained by simulation and calculation. Finally the design of Resonant DC Link Converters is discussed and reconunendations made for the choice of resonant components based on the minimisation of overall losses. Comparisons are made between hard-switching and soft-switching converters in terms of loss and harmonic performance, in an attempt to quantify the benefits which may be obtained by the application of soft-switching.

This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since FPGAs are prone to soft errors caused by radiation, and AES is highly sensitive to errors, reliable architectures are of significant concern. Energetic particles hitting a device can flip bits in FPGA SRAM cells controlling all aspects of the implementation. Unlike previous research, heterogeneous error detection techniques based on properties of the circuit and functionality are used to provide adequate reliability at the lowest possible cost. The use of dual ported block memory for SubBytes, duplication for the control circuitry, and a new enhanced parity technique for MixColumns is proposed. Previous parity techniques cover single errors in datapath registers, however, soft errors can occur in the control circuitry as well as in SRAM cells forming the combinational logic and routing. In this research, propagation of single errors is investigated in the routed netlist. Weaknesses of the previous parity techniques are identified. Architectural redesign at the register-transfer level is introduced to resolve undetected single errors in both the routing and the combinational logic. Reliability of the AES implementation is not only a critical issue in large scale FPGA-based systems but also at both higher altitudes and in space applications where there are a larger number of energetic particles. Thus, this research is important for providing efficient soft error resistant design in many current and future secure applications.