The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

In this thesis, we consider the problem of designing space-time block codes that have low maximum-likelihood (ML) decoding complexity. We present a unified framework for determining the worst-case ML decoding complexity of space-time block codes. We use this framework to not only determine the worst-case ML decoding complexity of our own constructions, but also to show that some popular constructions of space-time block codes have lower ML decoding complexity than was previously known. Recognizing the practical importance of the two transmit and two receive antenna system, we propose the asymmetric golden code, which is designed specifically for low ML decoding complexity. The asymmetric golden code has the lowest decoding complexity compared to previous constructions of space-time codes, regardless of whether the channel varies with time. We also propose the embedded orthogonal space-time codes, which is a family of codes for an arbitrary number of antennas, and for any rate up to half the number of antennas. The family of embedded orthogonal space-time codes is the first general framework for the construction of space-time codes with low-complexity decoding, not only for rate one, but for any rate up to half the number of transmit antennas. Simulation results for up to six transmit antennas show that the embedded orthogonal space-time codes are simultaneously lower in complexity and lower in error probability when compared to some of the most important constructions of space-time block codes with the same number of antennas and the same rate larger than one. Having considered the design of space-time block codes with low ML decoding complexity on the transmitter side, we also develop efficient algorithms for ML decoding for the golden code, the asymmetric golden code and the embedded orthogonal space-time block codes on the receiver side. Simulations of the bit-error rate performance and decoding complexity of the asymmetric golden code and embedded orthogonal codes are used to demonstrate their attractive performance-complexity tradeoff.

The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 131-134). Also available in electronic format on the Internet.

Thesis (Ph.D.)--University of Delaware, 2005. / Principal faculty adviser: Xiang-Gen Xia, Dept. of Electrical & Computer Engineering. Includes bibliographical references.

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Multiple antenna techniques are used to increase the robustness and performance of wireless networks. Multiple antenna techniques can achieve diversity and increase bandwidth efficiency when specially designed channel codes are used at the scheme’s transmitter. These channel codes can be designed in the space, time and frequency domain. These specially designed channel codes in the space and time domain are actually designed for flat fading channels and in frequency selective fading channel, their performance may be degraded. To counteract this possible performance degradation in frequency selective fading channel, two main approaches can be applied to mitigate the effect of the symbol interference due to the frequency selective fading channel. These approaches are multichannel equalisation and orthogonal frequency division multiplexing (OFDM). In this thesis, a multichannel equalisation technique and OFDM were applied to channel codes specially designed for multiple antenna systems. An optimum receiver was proposed for super-orthogonal space-time trellis codes in a multichannel equalised frequency selective environment. Although the proposed receiver had increased complexity, the diversity order is still the same as compared to the code in a flat fading channel. To take advantage of the multipath diversity possible in a frequency selective fading channel, super-orthogonal block codes were employed in an OFDM environment. A new kind of super-orthogonal block code was proposed in this thesis. Super-orthogonal space-frequency trellis-coded OFDM was proposed to take advantage of not only the possible multipath diversity but also the spatial diversity for coded OFDM schemes. Based on simulation results in this thesis, the proposed coded OFDM scheme performs better than all other coded OFDM schemes (i.e. space time trellis-coded OFDM, space-time block coded OFDM, space-frequency block coded OFDM and super-orthogonal space-time trellis-coded OFDM). A simplified channel estimation algorithm was proposed for two of the coded OFDM schemes, which form a broad-based classification of coded OFDM schemes, i.e. trelliscoded schemes and block-coded schemes. Finally in this thesis performance analysis using the Gauss Chebychev quadrature technique as a way of validating simulation results was done for super-orthogonal block coded OFDM schemes when channel state information is known and when it is estimated. The results obtained show that results obtained via simulation and analysis are asymptotic and therefore the proposed analysis technique can be use to obtain error rate values for different SNR region instead of time consuming simulation. / Thesis (PhD)--University of Pretoria, 2012. / Electrical, Electronic and Computer Engineering / unrestricted

M. Tech. Electrical Engineering. / Discusses MIMO systems have been hailed for the benefits of enhancing the reliability of the wireless communication link and increasing of the channel capacity, however the complexity of MIMO encoding and decoding algorithms increases considerably with the number of antennas. This research aims to suggest an optimisation approach to a reduced complexity implementation of the Alamouti 4×2 STBC. This is achieved by considering the FPGA parallelisation of the conditionally optimised ML decoding algorithm. The above problem can be divided into two subproblems. 1. The ML decoding of the Double Alamouti 4×2 STBC has a high computational cost when an exhaustive search is performed on the signal constellation for M-ary QAM. 2. Though the conditionally optimised ML decoding leads to less computational complexity compared to the full generic ML detection algorithm, the practical implementation remains unattractive for wireless systems.

M. Tech. Electrical Engineering. / Applies conditional optimisation to ML decoding of perfect STBCs, it is hypothesised that the obtained algorithms have reduced complexity and exhibit high DLP and TLP that can be exploited to map them on low-power multi-core SIMD processors, and possibly to reduce their runtimes and allow their real-time execution in a 4G wireless system.