At Saab Dynamics AB there are a number of projects where cameras are an important part of a sensor system. Examples of such projects are monitoring for civil security and 3D mapping, where several cameras are used. The cameras can for example be located in airplanes, helicopters or cars and therefore it is important to have a robust function for recording data. One way to achieve a quick recording with sufficient storage size is to use SATA flash disks. To reduce the size and power consumption of the recording equipment and to enable project-specific adaptations it is desirable to use an FPGA as an interface to SATA devices. This thesis concerns the development of such an interface implemented on an FPGA. The theory behind the SATA interconnect standard is described along with the design work and its challenges.

This master's thesis focuses on designing and implementing a framework that would offer basic program resources for application development on hardware platform FITkit Minerva. First part of this work focuses on designing a data channel between PC and the kit for which the USB interface was used. Next part focuses on implementing a channel between an ARM based microcontroller and FPGA Xilinx Spartan-6. That led to creating a special system inside FPGA that allows adding new HW components that communicate with the microcontroller, which can be used for implementing HW acceleration techniques. Another outcome of this work is a debugging interface that allows to program and debug FPGA using development environment Xilinx ISE without a need of the original Xilinx JTAG adapter. This was achieved by using the XVC protocol that allows to create a custom JTAG adapter that in this case was implemented in the software of the microcontroller.

The submitted thesis is concerned with a design of the multiplicator of memory cards. The basic focus of this thesis is the analysis of individual system components and adjustment of the existing arrangement. The analysis describes the existing arrangement of the multiplicator and deals with the potential of individual components. Adjustment of the existing arrangement includes definitions and processes of the individual multiplicator components design to the achievement of optimal performance. Operating of the multiplicator is fully controlled by a PC.

The master’s thesis deals with the design of modulator OFDM in the FPGA circuit. The thesis describes basic attributes of modulation OFDM, its pros and cons. With the help of created block level scheme, it describes all the components of the processing of the data signal on its way from the transmitter to the receiver. The Atlys Spartan-6 Development Board has been chosen for the implementation of the modulator. The other part of thesis is the design and realization of the analog-digital interface for the modulator OFDM. The interface consists of PCB, which is connected to the development board using expansion connector. The board is assembled with all the parts required for transmitting the signal as well as consecutive receiving, the description of used solutions is also a part of this master’s thesis. Proper function of both designed parts was verified using hardware co-simulation.

The modern embedded system is getting more complicated due to the functional requirements of the system are rapidly increasing. The modern system must have more reliable, as it deals with a lot of data. The distributed systems are used in variety technologies field due to it has more reliable than single control unit. It can transfer task to other processing unit when the one part of system failed while the single control unit failed cause the system to stop operate. The FPGA are being used increasingly in the distributed system due to the benefit of FPGA over microcontroller and ASIC. FPGA is flexible than ASIC due to the ability to reconfiguration its function. FPGA processes the data in parallel, therefore, it computes the data faster than the microcontroller that computes the data in concurrence. The flexibility of FPGA supports the development of reliable distributed system. When one of FPGA failed, the other FPGA can reconfiguration itself to operate on the task of the failed FPGA. The method to reconfigure the FPGA structure is a process of loading new bitstream file into FPGA. For generating variety configurations of distributed system. The developer must develop number of bitstream file according to number of reconfiguration designs. Although the FPGA is flexible and can reconfiguration anytime, the development process of configuration file is a redundancy workload. One FPGA design structure equals one configuration file. This project focus on reduce the redundancy workload, therefore, it can reduce the development time and make the development project launching faster. This virtual partial reconfiguration framework is developed to assist the developer in generating many configuration files without coding. The framework will determine all possible combination of modules and generates all combination design files. One set of the design contain the VHDL file and UCF file. The developer can use these files to synthesise in FPGA vendor development tool and generate bitstream. This virtual partial reconfiguration framework also provides the partial reconfiguration benefits except runtime reconfiguration.